Works matching DE "RISC microprocessors"
Results: 21
Competition between Alliance Blocks: The Case of the RISC Microprocessor Technology.
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- Organization Studies, 2001, v. 22, n. 1, p. 1, doi. 10.1177/017084060102200101
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Investigation of FPGA based 32-bit RISC-Modulation Processor.
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- International Journal of Computer Information Systems & Industrial Management Applications, 2018, v. 10, p. 227
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New Architecture for EIA-709.1 Protocol Implementation.
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- GSTF Journal on Computing, 2011, v. 1, n. 2, p. 180, doi. 10.5176/2010-2283_1.2.57
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Experiment Centric Teaching for Reconfigurable Processors.
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- International Journal of Reconfigurable Computing, 2011, p. 1, doi. 10.1155/2011/952560
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Reduced-Precision Redundancy on FPGAs.
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- International Journal of Reconfigurable Computing, 2011, p. 1, doi. 10.1155/2011/897189
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Design of an Intelligent Wireless Communication Module Based on ARM.
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- International Journal of Online Engineering, 2018, v. 14, n. 8, p. 67, doi. 10.3991/ijoe.v14i08.9177
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Parallel Integer Optimization for Crew Scheduling.
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- Annals of Operations Research, 2000, v. 99, n. 1-4, p. 141, doi. 10.1023/A:1019293017474
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An exercise on hardware/software codesign following the RISC model.
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- Computer Applications in Engineering Education, 2016, v. 24, n. 2, p. 305, doi. 10.1002/cae.21711
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An FPGA-based integrated environment for computer architecture.
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- Computer Applications in Engineering Education, 2013, v. 21, n. 1, p. 26, doi. 10.1002/cae.20448
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Design and implementation of a versatile cryptographic unit for RISC processors.
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- Security & Communication Networks, 2014, v. 7, n. 1, p. 36, doi. 10.1002/sec.555
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An Efficient Retargetable Simulator SIM-A for ASIP DSE and Validation with RISC and VLIW based Processors.
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- International Journal of Advanced Research in Computer Science, 2012, v. 3, n. 2, p. 11
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Web Based Smart Home Automation Control System Design.
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- International Journal of Contents, 2015, v. 11, n. 4, p. 70, doi. 10.5392/IJoC.2015.11.4.070
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Functional Tests for RISC-microprocessors.
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- Automation & Remote Control, 2004, v. 65, n. 11, p. 1847, doi. 10.1023/B:AURC.0000047898.43514.d0
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Microprocessor Based on the Minimal Hardware Principle.
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- Èlektronnoe Modelirovanie, 2019, v. 41, n. 6, p. 77, doi. 10.15407/emodel.10.06.077
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A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention.
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- Journal of Low Power Electronics & Applications, 2015, v. 5, n. 2, p. 57, doi. 10.3390/jlpea5020057
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Register allocation and spilling using the expected distance heuristic.
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- Software: Practice & Experience, 2016, v. 46, n. 11, p. 1499, doi. 10.1002/spe.2393
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A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks.
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- Sensors (14248220), 2014, v. 14, n. 1, p. 416, doi. 10.3390/s140100416
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An Embedded Real-Time Red Peach Detection System Based on an OV7670 Camera, ARM Cortex-M4 Processor and 3D Look-Up Tables.
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- Sensors (14248220), 2012, v. 12, n. 10, p. 14129, doi. 10.3390/s121014129
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Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture.
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- Journal of Supercomputing, 2011, v. 57, n. 3, p. 314, doi. 10.1007/s11227-010-0409-z
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DESIGN AND VERIFICATION OF 16-BIT RISC PROCESSOR USING SYSTEMVERILOG.
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- i-Manager's Journal on Circuits & Systems, 2018, v. 6, n. 4, p. 38, doi. 10.26634/jcir.6.4.14864
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An Automatic Instruction-Level Parallelization of Machine Code.
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- Advances in Electrical & Computer Engineering, 2018, v. 18, n. 1, p. 27, doi. 10.4316/AECE.2018.01004
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