Pick the right-timing for low-power conversion.
- Published in:
- Electronics Systems & Software, 2005, v. 3, n. 5, p. 42, doi. 10.1049/ess:20050507
- By:
- Publication type:
- Article
Works matching DE "PIPELINED ADCs"
Results: 15
1
2
A high‐speed MIMO FFT processor with full hardware utilization.
- Published in:
- International Journal of Circuit Theory & Applications, 2018, v. 46, n. 8, p. 1534, doi. 10.1002/cta.2497
- By:
- Publication type:
- Article
3
Developing Model-Based Design Evaluation for Pipelined A/D Converters.
- Published in:
- Radioengineering, 2012, v. 21, n. 3, p. 898
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- Publication type:
- Article
4
MULTISCALING COEFFICIENTS TECHNIQUE FOR GAIN ERROR BACKGROUND CALIBRATION IN PIPELINED ADC.
- Published in:
- Journal of Circuits, Systems & Computers, 2014, v. 23, n. 3, p. -1, doi. 10.1142/S0218126614500340
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- Publication type:
- Article
5
PERFORMANCE CHARACTERIZATION OF PIPELINED S-BOX IMPLEMENTATIONS FOR THE ADVANCED ENCRYPTION STANDARD.
- Published in:
- Journal of Circuits, Systems & Computers, 2014, v. 23, n. 3, p. -1, doi. 10.1142/S0218126614500364
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- Publication type:
- Article
6
A DITHERING TECHNIQUE FOR SHA_LESS PIPELINED ADC.
- Published in:
- Journal of Circuits, Systems & Computers, 2014, v. 23, n. 1, p. 1, doi. 10.1142/S0218126614500066
- By:
- Publication type:
- Article
7
A HIGH SPEED LOW POWER LATCHED COMPARATOR FOR SHA-LESS PIPELINED ADC.
- Published in:
- Journal of Circuits, Systems & Computers, 2013, v. 22, n. 3, p. -1, doi. 10.1142/S0218126613500047
- By:
- Publication type:
- Article
8
ADC Non-Linearity Low-Cost Test Through a Simplified Double-Histogram Method.
- Published in:
- Journal of Electronic Testing, 2010, v. 26, n. 1, p. 47, doi. 10.1007/s10836-009-5130-6
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- Publication type:
- Article
9
Software pipelining for graphic processing unit acceleration: Partition, scheduling and granularity.
- Published in:
- International Journal of High Performance Computing Applications, 2016, v. 30, n. 2, p. 169, doi. 10.1177/1094342015585845
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- Publication type:
- Article
10
Constant twiddle factor multiplier sharing in multipath delay feedback parallel pipelined FFT processors.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2014, v. 50, n. 15, p. 1050, doi. 10.1049/el.2014.1186
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- Publication type:
- Article
11
Pipelined adders for ultralow-power wearables.
- Published in:
- Turkish Journal of Electrical Engineering & Computer Sciences, 2019, v. 27, n. 1, p. 153, doi. 10.3906/elk-1711-211
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- Publication type:
- Article
12
Early Termination and Pipelining for Hardware Implementation of Fast H.264 Intraprediction Targeting Mobile HD Applications.
- Published in:
- EURASIP Journal on Advances in Signal Processing, 2008, p. 1, doi. 10.1155/2008/542735
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- Publication type:
- Article
13
Achievable ADC Performance by Postcorrection Utilizing Dynamic Modeling of the Integral Nonlinearity.
- Published in:
- EURASIP Journal on Advances in Signal Processing, 2008, p. 1, doi. 10.1155/2008/497187
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- Publication type:
- Article
14
ADC z w pełni różnicowym integratorem w trybie prądowym.
- Published in:
- Przegląd Elektrotechniczny, 2018, v. 94, n. 9, p. 22, doi. 10.15199/48.2018.09.05
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- Publication type:
- Article
15
Hardware architecture and optimisation of FPP particle PHD filter for multi-target tracking in cyber-physical systems.
- Published in:
- IET Control Theory & Applications (Wiley-Blackwell), 2017, v. 11, n. 11, p. 1830, doi. 10.1049/iet-cta.2016.1405
- By:
- Publication type:
- Article