Works matching DE "PERFORMANCE of multiprocessors"

Results: 17

Energy efficient mapping on manycore with dynamic and partial reconfiguration: Application to a smart camera.

Published in:

International Journal of Circuit Theory & Applications, 2018, v. 46, n. 9, p. 1648, doi. 10.1002/cta.2508

By:

Bonamy, Robin;
Bilavarn, Sébastien;
Muller, Fabrice;
Duhem, François;
Heywood, Simon;
Millet, Philippe;
Lemonnier, Fabrice

Publication type:

Article

Conditional Diagnosability of Burnt Pancake Networks Under the PMC Model.

Published in:

Computer Journal, 2016, v. 59, n. 1, p. 91, doi. 10.1093/comjnl/bxv066

By:

SULIN SONG;
SHUMING ZHOU;
XIAOYAN LI

Publication type:

Article

Bandwidth Adaptive Cache Coherence Optimizations for Chip Multiprocessors.

Published in:

International Journal of Parallel Programming, 2014, v. 42, n. 3, p. 435, doi. 10.1007/s10766-013-0247-8

By:

Kayi, Abdullah;
Serres, Olivier;
El-Ghazawi, Tarek

Publication type:

Article

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer.

Published in:

Journal of Low Power Electronics & Applications, 2017, v. 7, n. 2, p. 14, doi. 10.3390/jlpea7020014

By:

Ofori-Attah, Emmanuel;
Bhebhe, Washington;
Agyeman, Michael Opoku

Publication type:

Article

Parallel consistency model for global constraints based on centralized storage.

Published in:

Application Research of Computers / Jisuanji Yingyong Yanjiu, 2013, v. 30, n. 11, p. 3314, doi. 10.3969/j.issn.1001-3695.2013.11.027

By:

CAO Yan;
WEI Qiang;
WANG Qing-xian;
DING Wen-bo

Publication type:

Article

Use of saccadic latency for visual inspection system.

Published in:

Human Factors & Ergonomics in Manufacturing & Service Industries, 2012, v. 22, n. 4, p. 296, doi. 10.1002/hfm.20276

By:

Kotani, Kentaro;
Nakajima, Akira;
Asao, Takafumi;
Horii, Ken

Publication type:

Article

Computation planning in multiprocessor real time automated control systems with an additional resource.

Published in:

Automation & Remote Control, 2015, v. 76, n. 3, p. 487, doi. 10.1134/S0005117915030121

By:

Furugyan, M.

Publication type:

Article

Fat-tree-based optical networks-on-chip with WDM: crosstalk noise exploiting.

Published in:

IET Optoelectronics (Wiley-Blackwell), 2019, v. 13, n. 2, p. 85, doi. 10.1049/iet-opt.2018.5070

By:

Jingping Zhang;
Shujian Wang;
Yichen Ye;
Yuzhu Liu;
Gaofeng Pan;
Jiliang Zhang;
Yiyuan Xie;
Yong Liu

Publication type:

Article

Probabilistic elements in analysis of performance of multiprocessor systems.

Published in:

Bulletin of the Polish Academy of Sciences: Technical Sciences, 2014, v. 62, n. 4, p. 765, doi. 10.2478/bpasts-2014-0083

By:

Taborek, K.;
Hrynkiewicz, E.

Publication type:

Article

PS directory: a scalable multilevel directory cache for CMPs.

Published in:

Journal of Supercomputing, 2015, v. 71, n. 8, p. 2847, doi. 10.1007/s11227-014-1332-5

By:

Valls, Joan;
Ros, Alberto;
Sahuquillo, Julio;
Gómez, María

Publication type:

Article

Power-efficient prefetching on GPGPUs.

Published in:

Journal of Supercomputing, 2015, v. 71, n. 8, p. 2808, doi. 10.1007/s11227-014-1331-6

By:

Falahati, Hajar;
Hessabi, Shaahin;
Abdi, Mania;
Baniasadi, Amirali

Publication type:

Article

An analytical study of resource division and its impact on power and performance of multi-core processors.

Published in:

Journal of Supercomputing, 2014, v. 68, n. 3, p. 1265, doi. 10.1007/s11227-014-1086-0

By:

Vijayalakshmi, Saravanan;
Anpalagan, Alagan;
Kothari, D.;
Woungang, Isaac;
Obaidat, Mohammad

Publication type:

Article

PREDICTING THE PERFORMANCE MEASURES OF A 2-DIMENSIONAL MESSAGE PASSING MULTIPROCESSOR ARCHITECTURE BY USING MACHINE LEARNING METHODS.

Published in:

Neural Network World, 2015, n. 3, p. 241, doi. 10.14311/NNW.2015.25.013

By:

Akay, M. F.;
Aci, Ç. İ.;
Abut, F.

Publication type:

Article

A SIMULATION MODEL FOR THE PERFORMANCE EVALUATION OF HYBRID INTERCONNECTION ARCHITECTURES.

Published in:

International Journal of Advanced Research in Computer Science, 2018, v. 9, n. 2, p. 604, doi. 10.26483/ijarcs.v9i2.5831

By:

Gautam, Savita;
Bansal, Nitin;
Samad, Abdus

Publication type:

Article

EVALUATION OF OPENMP OPTIMIZATION IN HETEROGENEOUS COMPUTING MODE BY CODE OFFLOADING ON INTEL XEON PHI CO-PROCESSOR.

Published in:

International Journal of Advanced Research in Computer Science, 2018, v. 9, n. 2, p. 460, doi. 10.26483/ijarcs.v9i2.5746

By:

Chauhan, Kajal;
Bhensdadia, C. K.;
Potdar, M. B.

Publication type:

Article

STUDY OF MEMORY ORGANIZATION AND MULTIPROCESSOR SYSTEM - USING THE CONCEPT OF DISTRIBUTED SHARED MEMORY, MEMORY CONSISTENCY MODEL AND SOFTWARE BASED DSM.

Published in:

International Journal of Advanced Research in Computer Science, 2017, v. 8, n. 7, p. 1069, doi. 10.26483/ijarcs.v8i7.4406

By:

Kumari, Dhara;
Kaushik, Sarita;
Sharma, Rajni

Publication type:

Article

Test Structure for L1 Cache in Tiled CMPs.

Published in:

IAENG International Journal of Computer Science, 2016, v. 43, n. 3, p. 123

By:

Saha, Mousumi;
Sikdar, Biplab K.

Publication type:

Article