Works matching DE "LOGIC circuit synthesis (Electronic design)"
Results: 19
Novel Verification Method for Timing Optimization Based on DPSO.
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- VLSI Design, 2018, p. 1, doi. 10.1155/2018/8258397
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Quantum circuit physical design flow for 2D nearest-neighbor architectures.
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- International Journal of Circuit Theory & Applications, 2017, v. 45, n. 7, p. 989, doi. 10.1002/cta.2335
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- Article
Physical synthesis of quantum circuits using templates.
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- Quantum Information Processing, 2016, v. 15, n. 10, p. 4117, doi. 10.1007/s11128-016-1377-x
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- Article
Low-complexity motion estimation design using modified XOR function.
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- Multimedia Tools & Applications, 2016, v. 75, n. 24, p. 16809, doi. 10.1007/s11042-015-2948-z
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- Article
The Algorithm for Reversible Circuits Synthesis.
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- International Journal of Electronics & Telecommunications, 2020, v. 66, n. 2, p. 281, doi. 10.24425/ijet.2020.131875
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SMTBDD: New Form of BDD for Logic Synthesis.
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- International Journal of Electronics & Telecommunications, 2016, v. 62, n. 1, p. 33, doi. 10.1515/eletel-2016-0004
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- Article
Impact of Low-Variability SOTB Process on Ultra-Low-Voltage Operation of 1 Million Logic Gates.
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- Journal of Low Power Electronics & Applications, 2015, v. 5, n. 2, p. 116, doi. 10.3390/jlpea5020116
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Modified Ternary Karnaugh Map and Logic Synthesis in Ternary Quantum Dot Cellular Automata.
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- IETE Journal of Research, 2016, v. 62, n. 6, p. 774, doi. 10.1080/03772063.2016.1176541
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- Article
Improved Synthesis of Generalized Parallel Counters on FPGAs Using Only LUTs.
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- Journal of Circuits, Systems & Computers, 2018, v. 27, n. 1, p. -1, doi. 10.1142/S0218126618500020
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Asynchronous Logic Implementation Based on Factorized DIMS.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500876
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Literal Decomposition for LUT-Oriented Asynchronous Dual-Rail Logic Synthesis.
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- Journal of Circuits, Systems & Computers, 2015, v. 24, n. 7, p. -1, doi. 10.1142/S0218126615501108
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Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations.
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- Journal of Circuits, Systems & Computers, 2015, v. 24, n. 3, p. -1, doi. 10.1142/S0218126615500395
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Logic Decomposition for PAL-Based CPLDs.
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- Journal of Circuits, Systems & Computers, 2015, v. 24, n. 3, p. -1, doi. 10.1142/S0218126615500425
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- Article
HARDWARE REDUCTION IN CPLD-BASED MOORE FSM.
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- Journal of Circuits, Systems & Computers, 2014, v. 23, n. 6, p. 1, doi. 10.1142/S0218126614500868
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Symbolic Functional Decomposition of Multivalued Functions.
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- Journal of Multiple-Valued Logic & Soft Computing, 2015, v. 24, n. 5-6, p. 425
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Symbolic Functional Decomposition of Multivalued Functions.
- Published in:
- Journal of Multiple-Valued Logic & Soft Computing, 2015, v. 24, n. 5, p. 425
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Reversible Logic Synthesis Based on Decision Diagram Variable Ordering.
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- Journal of Multiple-Valued Logic & Soft Computing, 2012, v. 19, n. 4, p. 325
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Decomposition of multi-output functions oriented to configurability of logic blocks.
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- Bulletin of the Polish Academy of Sciences: Technical Sciences, 2017, v. 65, n. 3, p. 317, doi. 10.1515/bpasts-2017-0036
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- Article
Dual synthesis of Petri net based application specific logic controllers with increased safety.
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- Bulletin of the Polish Academy of Sciences: Technical Sciences, 2016, v. 64, n. 3, p. 467, doi. 10.1515/bpasts-2016-0052
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- Article