Works matching DE "LOGIC circuit synthesis (Electronic design)"

Results: 19

Quantum circuit physical design flow for 2D nearest-neighbor architectures.

Published in:

International Journal of Circuit Theory & Applications, 2017, v. 45, n. 7, p. 989, doi. 10.1002/cta.2335

By:

Farghadan, Azim;
Mohammadzadeh, Naser

Publication type:

Article

Modified Ternary Karnaugh Map and Logic Synthesis in Ternary Quantum Dot Cellular Automata.

Published in:

IETE Journal of Research, 2016, v. 62, n. 6, p. 774, doi. 10.1080/03772063.2016.1176541

By:

Das, Kunal;
De, Debashis;
De, Mallika

Publication type:

Article

Physical synthesis of quantum circuits using templates.

Published in:

Quantum Information Processing, 2016, v. 15, n. 10, p. 4117, doi. 10.1007/s11128-016-1377-x

By:

Mirkhani, Zahra;
Mohammadzadeh, Naser

Publication type:

Article

Novel Verification Method for Timing Optimization Based on DPSO.

Published in:

VLSI Design, 2018, p. 1, doi. 10.1155/2018/8258397

By:

Chen, Chuandong;
Wei, Rongshan;
Wang, Shaohao;
Hu, Wei

Publication type:

Article

Improved Synthesis of Generalized Parallel Counters on FPGAs Using Only LUTs.

Published in:

Journal of Circuits, Systems & Computers, 2018, v. 27, n. 1, p. -1, doi. 10.1142/S0218126618500020

By:

Khurshid, Burhan

Publication type:

Article

Asynchronous Logic Implementation Based on Factorized DIMS.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500876

By:

Lemberski, Igor

Publication type:

Article

Literal Decomposition for LUT-Oriented Asynchronous Dual-Rail Logic Synthesis.

Published in:

Journal of Circuits, Systems & Computers, 2015, v. 24, n. 7, p. -1, doi. 10.1142/S0218126615501108

By:

Lemberski, Igor

Publication type:

Article

Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations.

Published in:

Journal of Circuits, Systems & Computers, 2015, v. 24, n. 3, p. -1, doi. 10.1142/S0218126615500395

By:

Zgheib, Grace;
Ouaiss, Iyad

Publication type:

Article

Logic Decomposition for PAL-Based CPLDs.

Published in:

Journal of Circuits, Systems & Computers, 2015, v. 24, n. 3, p. -1, doi. 10.1142/S0218126615500425

By:

Kania, Dariusz

Publication type:

Article

HARDWARE REDUCTION IN CPLD-BASED MOORE FSM.

Published in:

Journal of Circuits, Systems & Computers, 2014, v. 23, n. 6, p. 1, doi. 10.1142/S0218126614500868

By:

BARKALOV, ALEXANDER;
TITARENKO, LARYSA;
CIIMIELEWSKI, SŁAWOMIR

Publication type:

Article

The Algorithm for Reversible Circuits Synthesis.

Published in:

International Journal of Electronics & Telecommunications, 2020, v. 66, n. 2, p. 281, doi. 10.24425/ijet.2020.131875

By:

Skorupski, Andrzej;
Gracki, Krzysztof

Publication type:

Article

SMTBDD: New Form of BDD for Logic Synthesis.

Published in:

International Journal of Electronics & Telecommunications, 2016, v. 62, n. 1, p. 33, doi. 10.1515/eletel-2016-0004

By:

Kubica, Marcin;
Kania, Dariusz

Publication type:

Article

Impact of Low-Variability SOTB Process on Ultra-Low-Voltage Operation of 1 Million Logic Gates.

Published in:

Journal of Low Power Electronics & Applications, 2015, v. 5, n. 2, p. 116, doi. 10.3390/jlpea5020116

By:

Yasuhiro Ogasahara;
Tadashi Nakagawa;
Toshihiro Sekigawa;
Hanpei Koike;
Toshiyuki Tsutsumi

Publication type:

Article

Symbolic Functional Decomposition of Multivalued Functions.

Published in:

Journal of Multiple-Valued Logic & Soft Computing, 2015, v. 24, n. 5-6, p. 425

By:

DENIZIAK, STANISLAW;
WISNIEWSKIU, MARIUSZ

Publication type:

Article

Symbolic Functional Decomposition of Multivalued Functions.

Published in:

Journal of Multiple-Valued Logic & Soft Computing, 2015, v. 24, n. 5, p. 425

By:

DENIZIAK, STANISLAW;
WISNIEWSKI, MARIUSZ

Publication type:

Article

Reversible Logic Synthesis Based on Decision Diagram Variable Ordering.

Published in:

Journal of Multiple-Valued Logic & Soft Computing, 2012, v. 19, n. 4, p. 325

By:

FEINSTEIN, DAVID Y.;
THORNTON, MITCHELL A.

Publication type:

Article

Decomposition of multi-output functions oriented to configurability of logic blocks.

Published in:

Bulletin of the Polish Academy of Sciences: Technical Sciences, 2017, v. 65, n. 3, p. 317, doi. 10.1515/bpasts-2017-0036

By:

KUBICA, M.;
KANIA, D.

Publication type:

Article

Dual synthesis of Petri net based application specific logic controllers with increased safety.

Published in:

Bulletin of the Polish Academy of Sciences: Technical Sciences, 2016, v. 64, n. 3, p. 467, doi. 10.1515/bpasts-2016-0052

By:

TKACZ, J.;
BUKOWIEC, A.;
ADAMSKI, M.

Publication type:

Article

Low-complexity motion estimation design using modified XOR function.

Published in:

Multimedia Tools & Applications, 2016, v. 75, n. 24, p. 16809, doi. 10.1007/s11042-015-2948-z

By:

AlQaralleh, Esam;
Abu-Sharkh, Osama

Publication type:

Article