Year-long 500°C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits.
- Published in:
- Journal of Microelectronic & Electronic Packaging, 2018, v. 15, n. 4, p. 163, doi. 10.4071/imaps.729648
- By:
- Publication type:
- Article
Works matching DE "JUNCTION gate field effect transistors"
Results: 5
1
2
Analytical model for the double-gate JFET applied to SiC power JFETs.
- Published in:
- International Journal of Modelling & Simulation, 2022, v. 42, n. 1, p. 9, doi. 10.1080/02286203.2020.1808775
- By:
- Publication type:
- Article
3
Junctionless II--gate transistor with indium gallium arsenide channel.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2013, v. 49, n. 6, p. 1, doi. 10.1049/el.2012.4535
- By:
- Publication type:
- Article
4
Influence of Gate Material and Process on Junctionless FET Subthreshold Performance.
- Published in:
- International Journal of Electrical & Computer Engineering (2088-8708), 2016, v. 6, n. 2, p. 895, doi. 10.11591/ijece.v6i2.407
- By:
- Publication type:
- Article
5
Analytical and experimental determination of the parasitic parameters in high-frequency inductor.
- Published in:
- Bulletin of the Polish Academy of Sciences: Technical Sciences, 2017, v. 65, n. 1, p. 107, doi. 10.1515/bpasts-2017-0013
- By:
- Publication type:
- Article