A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 2, p. 137, doi. 10.1007/s10836-016-5573-5
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- Publication type:
- Article
Works matching DE "INTEGRATED memory circuits"
Results: 10
1
2
FELINE MICROCHIP: AN EXERCISE IN THE SOCIOLOGY OF DOCUMENTALITY.
- Published in:
- Monist, 2014, v. 97, n. 2, p. 236
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- Publication type:
- Article
3
Low-Power Multimodal Switch for Leakage Reduction and Stability Improvement in SRAM Cell.
- Published in:
- Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ), 2016, v. 41, n. 8, p. 2945, doi. 10.1007/s13369-016-2047-0
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- Publication type:
- Article
4
Different Casues For Reduction Of Lekage Current In Sram: A State Of The Art.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2020, v. 2, n. 1, p. 18, doi. 10.31838/jvcs/02.01.05
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- Publication type:
- Article
5
PERFORMANCE PARAMETERS OF LOW POWER SRAM CELLS: A REVIEW.
- Published in:
- i-Manager's Journal on Circuits & Systems, 2017, v. 6, n. 1, p. 25
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- Publication type:
- Article
6
SRAM WRITE OPERATION USING WRITE ASSIST CIRCUIT TECHNIQUE AT LOW SUPPLY VOLTAGES.
- Published in:
- i-Manager's Journal on Circuits & Systems, 2016, v. 4, n. 4, p. 1, doi. 10.26634/jcir.4.4.12392
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- Publication type:
- Article
7
Ultra-Fast Current Mode Sense Amplifier for Small $$I_{\mathrm{CELL}}$$ SRAM in FinFET with Improved Offset Tolerance.
- Published in:
- Circuits, Systems & Signal Processing, 2016, v. 35, n. 9, p. 3066, doi. 10.1007/s00034-015-0199-x
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- Publication type:
- Article
8
Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications.
- Published in:
- Circuits, Systems & Signal Processing, 2016, v. 35, n. 2, p. 385, doi. 10.1007/s00034-015-0086-5
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- Publication type:
- Article
9
The Role of Physics in the Development of Microelectronics (Part 3).
- Published in:
- Electrotehnica, Electronica, Automatica, 2014, v. 62, n. 2, p. 53
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- Publication type:
- Article
10
Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology.
- Published in:
- International Journal of Circuit Theory & Applications, 2017, v. 45, n. 11, p. 1647, doi. 10.1002/cta.2280
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- Publication type:
- Article