Works matching DE "INTEGRATED circuit yield"
Results: 9
Post-layout Redundant Via Insertion Approach Considering Multiple Via Configuration.
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- Circuits, Systems & Signal Processing, 2015, v. 34, n. 10, p. 3353, doi. 10.1007/s00034-015-0010-z
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- Article
Compensation Scheme of a 50 Ω Bond Wire Interconnect Using Time Domain Reflectometry.
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- Journal of Microelectronic & Electronic Packaging, 2011, v. 8, n. 3, p. 114, doi. 10.4071/imaps.301
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- Article
Reduction of PCB PDN Impedance and Radiated Emissions Using a Hybrid Technique with Absorbing Materials and Decoupling Capacitors.
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- Progress in Electromagnetics Research B, 2017, v. 77, p. 137, doi. 10.2528/pierb17041605
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- Article
Process and terminations variations aware stability criteria for microwave amplifiers.
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- International Journal of RF & Microwave Computer-Aided Engineering, 2013, v. 23, n. 6, p. 619, doi. 10.1002/mmce.20696
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- Article
Adjacency-Clustering and Its Application for Yield Prediction in Integrated Circuit Manufacturing.
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- Operations Research, 2018, v. 66, n. 6, p. 1571, doi. 10.1287/opre.2018.1741
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- Article
A Highly-Integrated Low-Noise MICS Band Receiver RF Front-End IC with AC-Coupled Current Mirror Amplifier.
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- Journal of Circuits, Systems & Computers, 2019, v. 28, n. 1, p. N.PAG, doi. 10.1142/S0218126619500105
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- Article
Performance Degradation Tolerance Analysis and Design for Effective Yield Enhancement.
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- Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 427, doi. 10.1007/s10836-015-5546-0
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- Article
A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models.
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- Journal of Electronic Testing, 2015, v. 31, n. 3, p. 255, doi. 10.1007/s10836-015-5528-2
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- Article
Gate Driver Integrated Circuit with Breakdown Protection for Switch-mode Power Amplifiers.
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- Automatika: Journal for Control, Measurement, Electronics, Computing & Communications, 2016, v. 57, n. 2, p. 506, doi. 10.7305/automatika.2016.10.1005
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- Article