Works matching DE "INTEGRATED circuit layout"

Results: 52

Low‐Voltage Operation of Ring Oscillators Based on Room‐Temperature‐Deposited Amorphous Zinc‐Tin‐Oxide Channel MESFETs.

Published in:

Advanced Electronic Materials, 2019, v. 5, n. 12, p. N.PAG, doi. 10.1002/aelm.201900548

By:

Lahr, Oliver;
Vogt, Sofie;
Wenckstern, Holger;
Grundmann, Marius

Publication type:

Article

Circuit design with Independent Double Gate Transistors.

Published in:

Advances in Radio Science, 2009, v. 7, p. 231, doi. 10.5194/ars-7-231-2009

By:

Weis, M.;
Emling, R.;
Schmitt-Landsiedel, D.

Publication type:

Article

Physical IC debug -- backside approach and nanoscale challenge.

Published in:

Advances in Radio Science, 2008, v. 6, p. 265, doi. 10.5194/ars-6-265-2008

By:

Boit, C.;
Schlangen, R.;
Glowacki, A.;
Kindereit, U.;
Kiyan, T.;
Kerst, U.;
Lundquist, T.;
Kasapi, S.;
Suzuki, H.

Publication type:

Article

Rolling Grey Prediction of Taiwan IC Design Industry.

Published in:

Journal of Grey System, 2004, v. 16, n. 2, p. 165

By:

Shih-Chi Chang;
Hsiao-Cheng Yu

Publication type:

Article

Lyapunov function construction for a power system including induction machine dynamic characteristics.

Published in:

Electrical Engineering in Japan, 2005, v. 151, n. 1, p. 34, doi. 10.1002/eej.10372

By:

Ishigame, Atsushi;
Taniguchi, Tsuneo

Publication type:

Article

Performance-driven placement procedure for low power.

Published in:

Electrical Engineering in Japan, 2005, v. 151, n. 1, p. 56, doi. 10.1002/eej.20057

By:

Yoshikawa, Masaya;
Terai, Hidekazu

Publication type:

Article

Performance Assessment of a Solar-Assisted Desiccant-Based Air Handling Unit Considering Different Scenarios.

Published in:

Energies (19961073), 2016, v. 9, n. 9, p. 724, doi. 10.3390/en9090724

By:

Angrisani, Giovanni;
Roselli, Carlo;
Sasso, Maurizio;
Tariello, Francesco;
Vanoli, Giuseppe Peter

Publication type:

Article

Local search algorithms for the min-max loop layout problem.

Published in:

Journal of the Operational Research Society, 2002, v. 53, n. 10, p. 1109, doi. 10.1057/palgrave.jors.2601269

By:

Bennell, J.A.;
Potts, C.N.;
Whitehead, J.D.

Publication type:

Article

The Steiner ratio for points on a triangular lattice.

Published in:

Orion, 2008, v. 24, n. 2, p. 185, doi. 10.5784/24-2-66

By:

de Wet, P. O.

Publication type:

Article

An Efficient Reverse Engineering Hardware Trojan Detector Using Histogram of Oriented Gradients.

Published in:

Journal of Electronic Testing, 2017, v. 33, n. 1, p. 93, doi. 10.1007/s10836-016-5631-z

By:

Nasr, Abdurrahman;
Abdulmageed, Mohamed

Publication type:

Article

Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology.

Published in:

Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 561, doi. 10.1007/s10836-015-5549-x

By:

Li, Lixiang;
Li, Yuanqing;
Wang, Haibin;
Liu, Rui;
Wu, Qiong;
Newton, Michael;
Ma, Yuan;
Chen, Li

Publication type:

Article

Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip.

Published in:

Journal of Electronic Testing, 2011, v. 27, n. 4, p. 429, doi. 10.1007/s10836-011-5213-z

By:

Han, Kihyuk;
Park, Joonsung;
Lee, Jae;
Chung, Jaeyong;
Byun, Eonjo;
Woo, Cheol-Jong;
Oh, Sejang;
Abraham, Jacob

Publication type:

Article

Ant Colony Algorithm for Energy Saving to Optimize Three-Dimensional Bonding Chips' Thermal Layout.

Published in:

Technologies (2227-7080), 2023, v. 11, n. 5, p. 122, doi. 10.3390/technologies11050122

By:

Sun, Bihao;
Yang, Peizhi;
Zhu, Zhiyuan

Publication type:

Article

POST LAYOUT OPTIMIZATION METHODS FOR STRUCTURED ASIC.

Published in:

Bulletin of the Transilvania University of Brasov, Series I: Engineering Sciences, 2008, v. 1, n. 50, p. 413

By:

Tulbure, T.;
Jipa, R.

Publication type:

Article

Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs.

Published in:

International Journal of Reconfigurable Computing, 2010, p. 1, doi. 10.1155/2010/697625

By:

Mirzaei, Shahnam;
Kastner, Ryan;
Hosangadi, Anup

Publication type:

Article

AN APPROACH FOR DETERMINING MOSFET SMALL-SIGNAL CIRCUIT MODEL PARAMETERS.

Published in:

Microwave Journal, 2008, v. 51, n. 10, p. 116

By:

Qian Wang;
Cheng Yuan;
Yasen Huang;
Jianjun Gao

Publication type:

Article

New Physical Connectivity Engine for Native High Frequency Interconnect Verification.

Published in:: Microwave Journal, 2004, v. 47, n. 8, p. 118
Publication type:: Article

A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation.

Published in:

VLSI Design, 2013, p. 1, doi. 10.1155/2013/529150

By:

Ching-Lung Su;
Tse-Min Chen;
Kuo-Hsuan Wu

Publication type:

Article

Faster and Energy-Efficient Signed Multipliers.

Published in:

VLSI Design, 2013, p. 1, doi. 10.1155/2013/495354

By:

Ramkumar, B.;
Kittur, Harish M.

Publication type:

Article

A High-Efficiency Monolithic DC-DC PFM Boost Converter with Parallel Power MOS Technique.

Published in:

VLSI Design, 2013, p. 1, doi. 10.1155/2013/643293

By:

Hou-Ming Chen;
Robert C. Chang;
Kuang-Hao Lin

Publication type:

Article

Closing the Gap Between Electrical and Physical Design Steps with an Analog IC Placement Optimizer Enhanced with Machine-Learning-Based Post-Layout Performance Regressors.

Published in:

Electronics (2079-9292), 2024, v. 13, n. 22, p. 4360, doi. 10.3390/electronics13224360

By:

Martins, Ricardo

Publication type:

Article

Design of decryption process for advanced encryption standard algorithm in system-on-chip.

Published in:

International Journal of Electrical & Computer Engineering (2088-8708), 2024, v. 14, n. 6, p. 6838, doi. 10.11591/ijece.v14i6.pp6838-6845

By:

Prathap, Joseph Anthony;
Raj, Mrinal;
Patnaik, Ritu

Publication type:

Article

Processing Integrated Circuit Layouts Using Python: A Case Study On Rapid Prototyping.

Published in:

2015

By:

Jagannathan, Srinivasan;
Sinenian, Nareg;
Starman, Jared

Publication type:

Case Study

Electromagnetic Hotspots Identification in Integrated Circuits.

Published in:

Progress in Electromagnetics Research Letters, 2019, v. 86, p. 121, doi. 10.2528/pierl19062601

By:

Kapoor, Dipesh;
Sangwan, Vivek;
Cher Ming Tan

Publication type:

Article

Exposed Layouts of the Butterfly Network.

Published in:

Journal of Interconnection Networks, 2001, v. 2, n. 2, p. 233, doi. 10.1142/S0219265901000348

By:

Litman, Ami

Publication type:

Article

Getting On-Board ATE Test Fixtures.

Published in:

EE: Evaluation Engineering, 2004, v. 43, n. 3, p. 18

By:

Lecklider, Tom

Publication type:

Article

Post-layout Redundant Via Insertion Approach Considering Multiple Via Configuration.

Published in:

Circuits, Systems & Signal Processing, 2015, v. 34, n. 10, p. 3353, doi. 10.1007/s00034-015-0010-z

By:

Kan, Tsang-Chi;
Ruan, Shanq-Jang;
Chang, Ting-Feng;
Yang, Shih-Hsien

Publication type:

Article

High-Precision Differential-Input Buffered and External Transconductance Amplifier for Low-Voltage Low-Power Applications.

Published in:

Circuits, Systems & Signal Processing, 2013, v. 32, n. 2, p. 453, doi. 10.1007/s00034-012-9470-6

By:

Khateb, Fabian;
Kaçar, Firat;
Khatib, Nabhan;
Kubánek, David

Publication type:

Article

Layout Techniques for Integrated Circuit Designers.

Published in:

2023

By:

Schindler, Fred

Publication type:

Book Review

Automation blues [Automated chip assembly].

Published in:

Electronics Systems & Software, 2007, v. 5, n. 1, p. 16, doi. 10.1049/ess:20070102

By:

Edwards, C.

Publication type:

Article

Fast track to power talks.

Published in:

Electronics Systems & Software, 2007, v. 5, n. 1, p. 24, doi. 10.1049/ess:20070104

By:

Edwards, C.

Publication type:

Article

Opening up the black box [IP encryption].

Published in:

Electronics Systems & Software, 2006, v. 4, n. 5, p. 16, doi. 10.1049/ess:20060503

By:

Dauman, A.

Publication type:

Article

Reliability concerns come to the designer.

Published in:: Electronics Systems & Software, 2005, v. 3, n. 5, p. 16, doi. 10.1049/ess:20050502
Publication type:: Article

Layout of the Cube-connected Cycles without Long Wires.

Published in:

Computer Journal, 2001, v. 44, n. 5, p. 374, doi. 10.1093/comjnl/44.5.374

By:

Guihai Chen;
Lau, Francis C. M.

Publication type:

Article

ILLUSTRATION OF AUTOMATIC DIGITAL SYNTHESIS FOR CAMELLIA-128 CIPHER ALGORITHM.

Published in:

Acta Technica Napocensis. Electronica-Telecomunicatii, 2012, v. 53, n. 1, p. 21

By:

Faragó, Paul;
Jackum, Thomas;
Böhm, Christoph;
Hofer, Maximilian

Publication type:

Article

Development of a Location Optimization Method for Embedded Components.

Published in:

International Journal of Applied Mechanics, 2022, v. 14, n. 6, p. 1, doi. 10.1142/S1758825122500661

By:

Liu, Dedao;
Chiu, Louis N. S.;
Davies, Christopher H. J.;
Yan, Wenyi

Publication type:

Article

Integer Linear Programming Models for Global Routing.

Published in:

INFORMS Journal on Computing, 2006, v. 18, n. 2, p. 137, doi. 10.1287/ijoc.1040.0127

By:

Behjat, Laleh;
Vannelli, Anthony;
Rosehart, William

Publication type:

Article

Yield Enhancement Techniques for 3D Memories by Redundancy Sharing among All Layers.

Published in:

ETRI Journal, 2012, v. 34, n. 3, p. 388, doi. 10.4218/etrij.12.0111.0643

By:

Joohwan Lee;
Kihyun Park;
Sungho Kang

Publication type:

Article

S-visibility problem in VLSI chip design.

Published in:

Turkish Journal of Electrical Engineering & Computer Sciences, 2017, v. 25, n. 5, p. 3960, doi. 10.3906/elk-1608-281

By:

EKANDARI, Marzieh;
YEGANEH, Mahdieh

Publication type:

Article

A new instantaneous model of MESFET and HEMT devices for large-signal circuit design.

Published in:

Microwave & Optical Technology Letters, 2001, v. 29, n. 3, p. 187, doi. 10.1002/mop.1124

By:

Cicolani, Maurizio;
Di Martino, Alberto;
D'Innocenzo, Silvio;
Pisa, Stefano;
Tommasino, Pasquale;
Trifiletti, Alessandro

Publication type:

Article

A High-level Synthesis Design Flow from ESL to RTL with Multi-parametric Optimization Objective.

Published in:

IETE Journal of Research, 2011, v. 57, n. 2, p. 172, doi. 10.4103/0377-2063.81741

By:

Sengupta, Anirban;
Sedaghat, Reza

Publication type:

Article

Cell-Based ESD Diodes with a Zigzag-Shaped Layout to Enhance the ESD Survival Level.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 2, p. 1, doi. 10.1142/S0218126617500232

By:

Son, Minoh;
Park, Changkun

Publication type:

Article

A COMBINED SIMPLEX–TRUST-REGION METHOD FOR ANALOG CIRCUIT OPTIMIZATION.

Published in:

Journal of Circuits, Systems & Computers, 2008, v. 17, n. 1, p. 123

By:

BŰRMEN, ÁRPÁD;
TUMA, TADEJ;
FAJFAR, IZTOK

Publication type:

Article

SYNTHESIS OF PROPERTY MONITORS FOR ONLINE FAULT DETECTION.

Published in:

Journal of Circuits, Systems & Computers, 2007, v. 16, n. 6, p. 943, doi. 10.1142/S0218126607004088

By:

MORIN-ALLORY, K.;
GASCARD, E.;
BORRIONE, D.

Publication type:

Article

Linear Bi-CMOS Transconductance for Gm-C Filter Applications.

Published in:

Journal of Circuits, Systems & Computers, 2002, v. 11, n. 3, p. 219, doi. 10.1142/S0218126602000409

By:

Lee, J.;
Hayatleh, K.;
Lidgey, F. J.;
Drew, J.

Publication type:

Article

A CNN-Specific Integrated Processor.

Published in:

EURASIP Journal on Advances in Signal Processing, 2009, p. 1, doi. 10.1155/2009/854241

By:

Malki, Suleyman;
Spaanenburg, Lambert

Publication type:

Article

METHOD FOR EVALUATING THE THROUGHPUT PERFORMANCE OF SHUTTLE BASED STORAGE AND RETRIEVAL SYSTEMS.

Published in:

Technical Gazette / Tehnički Vjesnik, 2016, v. 23, n. 3, p. 715, doi. 10.17559/TV-20141022121007

By:

Lerher, Tone;
Ekren, Banu Y.;
Sari, Zaki;
Rosi, Bojan

Publication type:

Article

GUI Structural Metrics.

Published in:: International Arab Journal of Information Technology (IAJIT), 2011, v. 8, n. 2, p. 124
Publication type:: Article

Performance Analysis of Banyan-Type Multistage Interconnection Networks Under Nonuniform Traffic Pattern.

Published in:

2005

By:

Mun, Youngsong

Publication type:

Editorial

IBM Scores 3D Chip Breakthrough.

Published in:: IT Professional, 2007, v. 9, n. 3, p. 4
Publication type:: Article