Works matching DE "INSTRUCTION set architecture"

Results: 20

An approach to minimizing the interpretation overhead in Dynamic Binary Translation.

Published in:

Journal of Supercomputing, 2012, v. 61, n. 3, p. 804, doi. 10.1007/s11227-011-0636-y

By:

Chen, Wei;
Chen, Dan;
Wang, Zhiying

Publication type:

Article

Debugging and programming a RISC-V processor, using the IEEE 1149.1 standard.

Published in:

Journal Applied Computing / Revista de Cómputo Aplicado, 2024, v. 8, n. 22, p. 1, doi. 10.35429/JCA.2023.21.7.1.9

By:

RICO-GARCÍA, Paulina;
YAÑEZ-VARGAS, Juan Israel;
PARRA-MICHEL, Ramón;
CONDE-ALMADA, Ernesto

Publication type:

Article

Debugging and programming a RISC-V processor, using the IEEE 1149.1 standard.

Published in:

Journal Applied Computing / Revista de Cómputo Aplicado, 2023, v. 7, n. 21, p. 1, doi. 10.35429/JCA.2023.21.7.1.9

By:

RICO-GARCÍA, Paulina;
YAÑEZ-VARGAS, Juan Israel;
PARRA-MICHEL, Ramón;
CONDE-ALMADA, Ernesto

Publication type:

Article

Understanding Evolutionary Potential in Virtual CPU Instruction Set Architectures.

Published in:

PLoS ONE, 2013, v. 8, n. 12, p. 1, doi. 10.1371/journal.pone.0083242

By:

Bryson, David M.;
Ofria, Charles

Publication type:

Article

(Ann. Phys. 4/2024).

Published in:: Annalen der Physik, 2024, v. 536, n. 4, p. 1, doi. 10.1002/andp.202470008
Publication type:: Article

Comprehensive analysis of energy efficiency and performance of ARM and RISC-V SoCs.

Published in:

Journal of Supercomputing, 2024, v. 80, n. 9, p. 12771, doi. 10.1007/s11227-024-05946-9

By:

Suárez, Daniel;
Almeida, Francisco;
Blanco, Vicente

Publication type:

Article

Efficient Processing-in-Memory System Based on RISC-V Instruction Set Architecture.

Published in:

Electronics (2079-9292), 2024, v. 13, n. 15, p. 2971, doi. 10.3390/electronics13152971

By:

Lim, Jihwan;
Son, Jeonghun;
Yoo, Hoyoung

Publication type:

Article

Performance Improvements via Peephole Optimization in Dynamic Binary Translation.

Published in:

Electronics (2079-9292), 2024, v. 13, n. 9, p. 1608, doi. 10.3390/electronics13091608

By:

Xie, Wenbing;
Luo, Qiaoling;
Tian, Xue;
Huang, Junyi;
Qi, Fengbin

Publication type:

Article

Real-Time Performance Benchmarking of RISC-V Architecture: Implementation and Verification on an EtherCAT-Based Robotic Control System.

Published in:

Electronics (2079-9292), 2024, v. 13, n. 4, p. 733, doi. 10.3390/electronics13040733

By:

Yoo, Taeho;
Choi, Byoung Wook

Publication type:

Article

Latency-Constrained Neural Architecture Search Method for Efficient Model Deployment on RISC-V Devices.

Published in:

Electronics (2079-9292), 2024, v. 13, n. 4, p. 692, doi. 10.3390/electronics13040692

By:

Xiang, Mingxi;
Ding, Rui;
Liu, Haijun;
Zhou, Xichuan

Publication type:

Article

PERFORMANCE EVALUATION OF BLAS ON THE TRIDENT PROCESSOR.

Published in:

Parallel Processing Letters, 2005, v. 15, n. 4, p. 407, doi. 10.1142/S0129626405002325

By:

Soliman, Mostafa I.;
Sedukhin, Stanislav G.

Publication type:

Article

Darwin3: a large-scale neuromorphic chip with a novel ISA and on-chip learning.

Published in:

National Science Review, 2024, v. 11, n. 5, p. 1, doi. 10.1093/nsr/nwae102

By:

Ma, De;
Jin, Xiaofei;
Sun, Shichun;
Li, Yitao;
Wu, Xundong;
Hu, Youneng;
Yang, Fangchao;
Tang, Huajin;
Zhu, Xiaolei;
Lin, Peng;
Pan, Gang

Publication type:

Article

DESIGN OF RISCV PROCESSOR USING VERILOG.

Published in:

i-Manager's Journal on Digital Signal Processing, 2024, v. 12, n. 1, p. 15, doi. 10.26634/jdp.12.1.20567

By:

E., JAYA;
B., MANEESHA;
G., SRIRAM;
G., SAI;
M., SIDDHU

Publication type:

Article

A Parallel Dynamic Binary Translator for Efficient Multi-Core Simulation.

Published in:

International Journal of Parallel Programming, 2013, v. 41, n. 2, p. 212, doi. 10.1007/s10766-012-0222-9

By:

Almer, Oscar;
Böhm, Igor;
Koch, Tobias;
Franke, Björn;
Kyle, Stephen;
Seeker, Volker;
Thompson, Christopher;
Topham, Nigel

Publication type:

Article

A Virtual Machine Platform Providing Machine Learning as a Programmable and Distributed Service for IoT and Edge On-Device Computing: Architecture, Transformation, and Evaluation of Integer Discretization.

Published in:

Algorithms, 2024, v. 17, n. 8, p. 356, doi. 10.3390/a17080356

By:

Bosse, Stefan

Publication type:

Article

CORPORATE RAIDING, SECRETS, AND THE BATTLE FOR DOMINATION OF THE COMPUTER CHIP INDUSTRY : AN ANALYSIS OF APPLE INC. V. RIVOS INC. ET AL.

Published in:

Business Law Review (15337421), 2024, v. 55, p. 1

By:

Davis, Wade S.;
Lundquist, Todd S.

Publication type:

Article

Design of a Ternary Logic Processor Using CNTFET Technology.

Published in:

Circuits, Systems & Signal Processing, 2024, v. 43, n. 9, p. 5809, doi. 10.1007/s00034-024-02726-x

By:

Gadgil, Sharvani;
Sandesh, Goli Naga;
Vudadha, Chetan

Publication type:

Article

A Survey of Virtualization Technologies: Towards a New Taxonomic Proposal.

Published in:

Revista Ingeniería e Investigación, 2022, v. 42, n. 3, p. 1, doi. 10.15446/ing.investig.97363

By:

Sepúlveda-Rodríguez, Luis E.;
Chavarro-Porras, Julio C.;
Sanabria-Ordoñez, John A.;
Castro, Harold E.;
Matthews, Jeanna

Publication type:

Article

An Overlay Accelerator of DeepLab CNN for Spacecraft Image Segmentation on FPGA.

Published in:

Remote Sensing, 2024, v. 16, n. 5, p. 894, doi. 10.3390/rs16050894

By:

Guo, Zibo;
Liu, Kai;
Liu, Wei;
Sun, Xiaoyao;
Ding, Chongyang;
Li, Shangrong

Publication type:

Article

PhD Abstracts.

Published in:: Journal of Functional Programming, 2024, v. 34, p. 1, doi. 10.1017/S0956796824000108
Publication type:: Article