Works matching DE "INSTRUCTION set architecture"
Results: 20
CORPORATE RAIDING, SECRETS, AND THE BATTLE FOR DOMINATION OF THE COMPUTER CHIP INDUSTRY : AN ANALYSIS OF APPLE INC. V. RIVOS INC. ET AL.
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- Business Law Review (15337421), 2024, v. 55, p. 1
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- Article
Design of a Ternary Logic Processor Using CNTFET Technology.
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- Circuits, Systems & Signal Processing, 2024, v. 43, n. 9, p. 5809, doi. 10.1007/s00034-024-02726-x
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- Article
(Ann. Phys. 4/2024).
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- Annalen der Physik, 2024, v. 536, n. 4, p. 1, doi. 10.1002/andp.202470008
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- Article
Darwin3: a large-scale neuromorphic chip with a novel ISA and on-chip learning.
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- National Science Review, 2024, v. 11, n. 5, p. 1, doi. 10.1093/nsr/nwae102
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A Survey of Virtualization Technologies: Towards a New Taxonomic Proposal.
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- Revista Ingeniería e Investigación, 2022, v. 42, n. 3, p. 1, doi. 10.15446/ing.investig.97363
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- Article
PERFORMANCE EVALUATION OF BLAS ON THE TRIDENT PROCESSOR.
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- Parallel Processing Letters, 2005, v. 15, n. 4, p. 407, doi. 10.1142/S0129626405002325
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- Article
PhD Abstracts.
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- Journal of Functional Programming, 2024, v. 34, p. 1, doi. 10.1017/S0956796824000108
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- Article
Debugging and programming a RISC-V processor, using the IEEE 1149.1 standard.
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- Journal Applied Computing / Revista de Cómputo Aplicado, 2024, v. 8, n. 22, p. 1, doi. 10.35429/JCA.2023.21.7.1.9
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Debugging and programming a RISC-V processor, using the IEEE 1149.1 standard.
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- Journal Applied Computing / Revista de Cómputo Aplicado, 2023, v. 7, n. 21, p. 1, doi. 10.35429/JCA.2023.21.7.1.9
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- Article
Efficient Processing-in-Memory System Based on RISC-V Instruction Set Architecture.
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- Electronics (2079-9292), 2024, v. 13, n. 15, p. 2971, doi. 10.3390/electronics13152971
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Performance Improvements via Peephole Optimization in Dynamic Binary Translation.
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- Electronics (2079-9292), 2024, v. 13, n. 9, p. 1608, doi. 10.3390/electronics13091608
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Real-Time Performance Benchmarking of RISC-V Architecture: Implementation and Verification on an EtherCAT-Based Robotic Control System.
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- Electronics (2079-9292), 2024, v. 13, n. 4, p. 733, doi. 10.3390/electronics13040733
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Latency-Constrained Neural Architecture Search Method for Efficient Model Deployment on RISC-V Devices.
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- Electronics (2079-9292), 2024, v. 13, n. 4, p. 692, doi. 10.3390/electronics13040692
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An Overlay Accelerator of DeepLab CNN for Spacecraft Image Segmentation on FPGA.
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- Remote Sensing, 2024, v. 16, n. 5, p. 894, doi. 10.3390/rs16050894
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- Article
Comprehensive analysis of energy efficiency and performance of ARM and RISC-V SoCs.
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- Journal of Supercomputing, 2024, v. 80, n. 9, p. 12771, doi. 10.1007/s11227-024-05946-9
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An approach to minimizing the interpretation overhead in Dynamic Binary Translation.
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- Journal of Supercomputing, 2012, v. 61, n. 3, p. 804, doi. 10.1007/s11227-011-0636-y
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- Article
DESIGN OF RISCV PROCESSOR USING VERILOG.
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- i-Manager's Journal on Digital Signal Processing, 2024, v. 12, n. 1, p. 15, doi. 10.26634/jdp.12.1.20567
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- Article
A Parallel Dynamic Binary Translator for Efficient Multi-Core Simulation.
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- International Journal of Parallel Programming, 2013, v. 41, n. 2, p. 212, doi. 10.1007/s10766-012-0222-9
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- Article
A Virtual Machine Platform Providing Machine Learning as a Programmable and Distributed Service for IoT and Edge On-Device Computing: Architecture, Transformation, and Evaluation of Integer Discretization.
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- Algorithms, 2024, v. 17, n. 8, p. 356, doi. 10.3390/a17080356
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- Article
Understanding Evolutionary Potential in Virtual CPU Instruction Set Architectures.
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- PLoS ONE, 2013, v. 8, n. 12, p. 1, doi. 10.1371/journal.pone.0083242
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- Article