Design and FPGA Implementation of Two-Dimensional Discrete Wavelet Transform Architectures Using Raster-Scan Method.
- Published in:
- Al-Rafadain Engineering Journal, 2014, v. 22, n. 2, p. 60
- By:
- Publication type:
- Article
Works matching DE "FIELD programmable gate arrays -- Design %26 construction"
Results: 14
1
2
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.
- Published in:
- Journal of Supercomputing, 2006, v. 38, n. 1, p. 3, doi. 10.1007/s11227-006-6719-5
- By:
- Publication type:
- Article
3
Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application.
- Published in:
- International Journal of Reconfigurable Computing, 2012, p. 1, doi. 10.1155/2012/507173
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- Publication type:
- Article
4
Multi-axis motion controller for robotic applications implemented on an FPGA.
- Published in:
- International Journal of Advanced Manufacturing Technology, 2013, v. 67, n. 9-12, p. 2367, doi. 10.1007/s00170-012-4656-4
- By:
- Publication type:
- Article
5
Efficient and high-performance pedestrian detector implementation for intelligent vehicles.
- Published in:
- IET Intelligent Transport Systems (Wiley-Blackwell), 2016, v. 10, n. 6, p. 438, doi. 10.1049/iet-its.2015.0239
- By:
- Publication type:
- Article
6
Design of IP core for IIC bus controller based on FPGA.
- Published in:
- Journal of Measurement Science & Instrumentation, 2015, v. 6, n. 1, p. 13, doi. 10.3969/j.issn.1674-8042.2015.01.003
- By:
- Publication type:
- Article
7
An FPGA Architecture for the Recovery of WPA/WPA2 Keys.
- Published in:
- Journal of Circuits, Systems & Computers, 2015, v. 24, n. 7, p. -1, doi. 10.1142/S0218126615501054
- By:
- Publication type:
- Article
8
Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA.
- Published in:
- Wireless Personal Communications, 2014, v. 76, n. 3, p. 569, doi. 10.1007/s11277-014-1725-z
- By:
- Publication type:
- Article
9
Dynamic tracking down-conversion signal processing method based on reference signal for grating heterodyne interferometer.
- Published in:
- Optical Engineering, 2012, v. 51, n. 8, p. 1, doi. 10.1117/1.OE.51.8.081512
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- Publication type:
- Article
10
Binary LDPC Codes Decoding Algorithm Based on MRF and FPGA Implementation.
- Published in:
- Telkomnika, 2016, v. 14, n. 4, p. 1383, doi. 10.12928/TELKOMNIKA.v14i4.4158
- By:
- Publication type:
- Article
11
Non-binary LDPC Decoder Design over Rayleigh Channel for FPGA Implementation.
- Published in:
- Telkomnika, 2016, v. 14, n. 4, p. 1376, doi. 10.12928/TELKOMNIKA.v14i4.4157
- By:
- Publication type:
- Article
12
Design, Simulation and FPGA Implementation of a Novel Router for Bulk Flow TCP in Optical IP Networks.
- Published in:
- IAENG International Journal of Computer Science, 2011, v. 38, n. 4, p. 343
- By:
- Publication type:
- Article
13
A PYRAMID-BASED BLOCK OF SKEWERS FOR PIXEL PURITY INDEX FOR ENDMEMBER EXTRACTION IN HYPERSPECTRAL IMAGERY.
- Published in:
- International Journal of High Speed Electronics & Systems, 2008, v. 18, n. 2, p. 469, doi. 10.1142/S0129156408005497
- By:
- Publication type:
- Article
14
RAFIA — Reliable ASIC/FPGA-based solutions for I&C applications.
- Published in:
- Nuclear Future, 2008, v. 4, n. 4, p. 204
- By:
- Publication type:
- Article