Works about FIELD programmable gate arrays
Results: 3219
Temporal Noise Reduction Algorithm with an Adaptive Threshold for Cooled Thermal Imaging Optoelectronic Systems.
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- Journal of Communications Technology & Electronics, 2024, v. 69, n. 4, p. 206, doi. 10.1134/S1064226924700268
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- Article
Field Programmable Gate Array (FPGA) Implementation of a Multi-Symbol Detection Algorithm with Reduced Matching Branches and Multiplexed Finite Impulse Response (FIR) Filters.
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- Applied Sciences (2076-3417), 2025, v. 15, n. 4, p. 2199, doi. 10.3390/app15042199
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An Improved LZO Compression Algorithm for FPGA Configuration Bitstream Files.
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- Computers, Materials & Continua, 2025, v. 82, n. 2, p. 3091, doi. 10.32604/cmc.2025.058688
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VCONV: A Convolutional Neural Network Accelerator for FPGAs.
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- Electronics (2079-9292), 2025, v. 14, n. 4, p. 657, doi. 10.3390/electronics14040657
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A Comparison of Reliability and Resource Utilization of Radiation Fault Tolerance Mechanisms in Spaceborne Electronic Systems.
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- Aerospace (MDPI Publishing), 2025, v. 12, n. 2, p. 152, doi. 10.3390/aerospace12020152
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- Article
Programmable Photonic Logic Array Based on Micro-Ring Resonators and All-Optical Modulation.
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- Micromachines, 2025, v. 16, n. 2, p. 238, doi. 10.3390/mi16020238
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Development of a Multi-Channel Ultra-Wideband Electromagnetic Transient Measurement System.
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- Sensors (14248220), 2025, v. 25, n. 4, p. 1159, doi. 10.3390/s25041159
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Adapting to the economics of SOC.
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- Solid State Technology, 2001, v. 44, n. 6, p. 14
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Implementation of a novel adaptive coding using VLSI architecture for data compression in image processing.
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- Multimedia Tools & Applications, 2024, v. 83, n. 36, p. 85801, doi. 10.1007/s11042-024-20055-8
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- Article
Circuit realization and FPGA-based implementation of a fractional-order chaotic system for cancellable face recognition.
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- Multimedia Tools & Applications, 2024, v. 83, n. 34, p. 81565, doi. 10.1007/s11042-023-15867-z
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- Article
Improving the hearing aid system using optimized variable bandwidth filter based on wolf optimization.
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- Multimedia Tools & Applications, 2024, v. 83, n. 33, p. 79503, doi. 10.1007/s11042-024-19748-x
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- Article
Fast data-independent KLT approximations based on integer functions.
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- Multimedia Tools & Applications, 2024, v. 83, n. 26, p. 67303, doi. 10.1007/s11042-024-18159-2
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Designing hardware for a robust high-speed cryptographic key generator based on multiple chaotic systems and its FPGA implementation for real-time video encryption.
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- Multimedia Tools & Applications, 2024, v. 83, n. 24, p. 64499, doi. 10.1007/s11042-023-17972-5
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- Article
FPGA implementation of deep learning architecture for kidney cancer detection from histopathological images.
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- Multimedia Tools & Applications, 2024, v. 83, n. 21, p. 60583, doi. 10.1007/s11042-023-17895-1
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- Article
Fire and blood detection system in disaster environment using UAV and FPGA.
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- Multimedia Tools & Applications, 2023, v. 82, n. 28, p. 43315, doi. 10.1007/s11042-023-15507-6
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A real-time omnidirectional target detection system based on FPGA.
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- Multimedia Tools & Applications, 2023, v. 82, n. 20, p. 30929, doi. 10.1007/s11042-023-14585-w
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- Article
Pullikolam assisted medical image watermarking on reconfigurable hardware.
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- Multimedia Tools & Applications, 2023, v. 82, n. 14, p. 21193, doi. 10.1007/s11042-023-14725-2
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Performance-oriented FPGA-based convolution neural network designs.
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- Multimedia Tools & Applications, 2023, v. 82, n. 14, p. 21019, doi. 10.1007/s11042-023-14537-4
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- Article
Study on versatile video coding multiple transform selection of hardware architecture based on FPGA.
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- Multimedia Tools & Applications, 2023, v. 82, n. 10, p. 14929, doi. 10.1007/s11042-022-14069-3
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- Article
Performance analysis of memory data layout for sub-block data access.
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- Multimedia Tools & Applications, 2023, v. 82, n. 5, p. 7229, doi. 10.1007/s11042-022-13564-x
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FPGA implementation of EFSME for high efficient video coding standard.
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- Multimedia Tools & Applications, 2022, v. 81, n. 23, p. 34087, doi. 10.1007/s11042-022-13051-3
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FPGA implementation of EFSME for high efficient video coding standard.
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- Multimedia Tools & Applications, 2022, v. 81, n. 22, p. 34087, doi. 10.1007/s11042-022-13051-3
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Image encryption with a Josephson junction model embedded in FPGA.
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- Multimedia Tools & Applications, 2022, v. 81, n. 17, p. 23819, doi. 10.1007/s11042-022-12400-6
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Software and hardware-based audio-video crypto steganalysis model for enhancing robustness and imperceptibility of secured data.
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- Multimedia Tools & Applications, 2022, v. 81, n. 15, p. 21047, doi. 10.1007/s11042-022-12353-w
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On FPGA implementation in medical secret image sharing with data hiding.
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- Multimedia Tools & Applications, 2022, v. 81, n. 13, p. 18755, doi. 10.1007/s11042-022-12451-9
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- Article
High Speed Area Optimized Hybrid DA Architecture for 2D-DTCWT.
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- International Journal of Image & Graphics, 2018, v. 18, n. 1, p. -1, doi. 10.1142/S0219467818500043
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FPGA-Based Multiplier-Less Log-Based Hardware Architectures for Hybrid Color Image Enhancement System.
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- International Journal of Image & Graphics, 2017, v. 17, n. 1, p. -1, doi. 10.1142/S0219467817500048
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RELIEF TEXTURE MAPPING ON FIELD PROGRAMMABLE GATE ARRAY.
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- International Journal of Image & Graphics, 2006, v. 6, n. 4, p. 641, doi. 10.1142/S021946780600246X
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- Article
Design of a novel CEM-FRM-based low-complexity channelised radar transmitter.
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- IET Radar, Sonar & Navigation (Wiley-Blackwell), 2021, v. 15, n. 12, p. 1643, doi. 10.1049/rsn2.12153
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Active elimination of DC bias current of a SiC based dual active bridge by controlling the dead time period.
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- IET Power Electronics (Wiley-Blackwell), 2024, v. 17, n. 14, p. 1960, doi. 10.1049/pel2.12753
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- Article
A hybrid level shifted carrier‐based PWM technique for modular multilevel converters.
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- IET Power Electronics (Wiley-Blackwell), 2021, v. 14, n. 13, p. 2219, doi. 10.1049/pel2.12173
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Fully FPGA‐based implementation of a modified control strategy for power electronic transformer in railway traction applications.
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- IET Power Electronics (Wiley-Blackwell), 2021, v. 14, n. 11, p. 1904, doi. 10.1049/pel2.12158
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PWM techniques for an asymmetric multilevel binary inverter: an FPGA‐based implementation.
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- IET Power Electronics (Wiley-Blackwell), 2021, v. 14, n. 8, p. 1529, doi. 10.1049/pel2.12131
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- Article
A field programmable gate array controlled high‐current pulsed source for airborne transient electromagnetic system.
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- IET Power Electronics (Wiley-Blackwell), 2021, v. 14, n. 7, p. 1313, doi. 10.1049/pel2.12095
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Parallel implementation of the auxiliary power system model of the electric locomotive for hardware-in-the-loop simulation.
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- IET Power Electronics (Wiley-Blackwell), 2019, v. 12, n. 13, p. 3521, doi. 10.1049/iet-pel.2019.0220
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- Article
Device-level modelling and FPGA-based real-time simulation of the power electronic system in fuel cell electric vehicle.
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- IET Power Electronics (Wiley-Blackwell), 2019, v. 12, n. 13, p. 3479, doi. 10.1049/iet-pel.2019.0101
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- Article
Lyapunov model predictive control to optimise computational burden, reference tracking and THD of three-phase four-leg inverter.
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- IET Power Electronics (Wiley-Blackwell), 2019, v. 12, n. 5, p. 1061, doi. 10.1049/iet-pel.2018.5732
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- Article
Modified model predictive torque control for a PMSM-drive with torque ripple minimisation.
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- IET Power Electronics (Wiley-Blackwell), 2019, v. 12, n. 5, p. 1033, doi. 10.1049/iet-pel.2018.5525
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- Article
Synchronous control strategy of dual five-level converters based on the improved SVPWM.
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- IET Power Electronics (Wiley-Blackwell), 2018, v. 11, n. 14, p. 2311, doi. 10.1049/iet-pel.2018.5564
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- Article
Efficient FPGA-based real-time implementation of an SVPWM algorithm for a delta inverter.
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- IET Power Electronics (Wiley-Blackwell), 2018, v. 11, n. 9, p. 1, doi. 10.1049/iet-pel.2017.0418
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- Article
Non-linear behavioural modelling of device-level transients for complex power electronic converter circuit hardware realisation on FPGA.
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- IET Power Electronics (Wiley-Blackwell), 2018, v. 11, n. 9, p. 1, doi. 10.1049/iet-pel.2017.0212
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- Article
Analysing the effects due to discontinuous output-voltage ripple in a digitally current-mode controlled boost converter.
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- IET Power Electronics (Wiley-Blackwell), 2018, v. 11, n. 6, p. 1055, doi. 10.1049/iet-pel.2017.0745
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- Article
High-accuracy multi-rate implementation of resonant integrator using FPGA.
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- IET Power Electronics (Wiley-Blackwell), 2017, v. 10, n. 3, p. 348, doi. 10.1049/iet-pel.2015.0702
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- Article
Fuzzy supervised online coactive neuro-fuzzy inference system-based rotor position control of brushless DC motor.
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- IET Power Electronics (Wiley-Blackwell), 2016, v. 9, n. 11, p. 2229, doi. 10.1049/iet-pel.2015.0919
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Ripple-reduced model predictive direct power control for active front-end power converters with extended switching vectors and time-optimised control.
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- IET Power Electronics (Wiley-Blackwell), 2016, v. 9, n. 9, p. 1914, doi. 10.1049/iet-pel.2015.0857
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- Article
Field programmable gate array implementation of a single-input fuzzy proportional-integral-derivative controller for DC-DC buck converters.
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- IET Power Electronics (Wiley-Blackwell), 2016, v. 9, n. 6, p. 1259, doi. 10.1049/iet-pel.2015.0688
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High-performance digital replica of analogue peak current mode control for DC-DC converter.
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- IET Power Electronics (Wiley-Blackwell), 2016, v. 9, n. 4, p. 809, doi. 10.1049/iet-pel.2015.0166
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- Article
Real-time simulation of modular multilevel converters for controller hardware-in-the-loop testing.
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- IET Power Electronics (Wiley-Blackwell), 2016, v. 9, n. 1, p. 42, doi. 10.1049/iet-pel.2015.0012
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Carrierless pulse width modulation strategy for multilevel inverters.
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- IET Power Electronics (Wiley-Blackwell), 2015, v. 8, n. 10, p. 2034, doi. 10.1049/iet-pel.2014.0742
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- Article
Active zero voltage switching tracking controller design for class E inverter to counteract the resonant components shifting.
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- IET Power Electronics (Wiley-Blackwell), 2015, v. 8, n. 10, p. 2016, doi. 10.1049/iet-pel.2014.0310
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