DESCRIPCIÓN MODULAR DE UN ESQUEMA DE CODIFICACIÓN CONCATENADO PARA CORRECCIÓN DE ERRORES CON PROGRAMACIÓN DE HARDWARE.
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- INGENIARE - Revista Chilena de Ingeniería, 2008, v. 16, n. 3, p. 310
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Works matching DE "ELECTRONIC decoder design %26 construction"
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Design and Implementation of Operation-Reduced LDPC Decoder Based on a Check Node Stopping Scheme.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 2, p. 1, doi. 10.1142/S0218126617500281
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MPCM: a hardware coder for super slow motion video sequences.
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- EURASIP Journal on Advances in Signal Processing, 2013, v. 2013, n. 1, p. 1, doi. 10.1186/1687-6180-2013-142
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