A Jitter Suppressed DLL-Based Clock Generator.
- Published in:
- Journal of the Korea Institute of Information & Communication Engineering, 2017, v. 21, n. 7, p. 1261, doi. 10.6109/jkiice.2017.21.7.1261
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- Publication type:
- Article
Works matching DE "DELAY-locked loops"
Results: 22
1
2
A Review on Circuit Simulation Techniques of Single-Event Transients and their Propagation in Delay Locked Loop.
- Published in:
- IETE Technical Review, 2017, v. 34, n. 3, p. 276, doi. 10.1080/02564602.2016.1184106
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- Publication type:
- Article
3
Impact of Control System Structure and Performance of Inventory Goods Flow System with Long-Variable Delay.
- Published in:
- Electronics & Electrical Engineering, 2018, v. 24, n. 1, p. 11, doi. 10.5755/j01.eie.24.1.14244
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- Publication type:
- Article
4
Low-power TDC scheme using DLL-based gray counter for infrared imagers.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2017, v. 53, n. 14, p. 922, doi. 10.1049/el.2017.0878
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- Publication type:
- Article
5
Two-step injection clock generation technique for fractional-N MDLL.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2016, v. 52, n. 21, p. 1746, doi. 10.1049/el.2016.2755
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- Publication type:
- Article
6
DLL-based signal conditioning system for SAW sensor with digital output.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2016, v. 52, n. 11, p. 893, doi. 10.1049/el.2016.0529
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- Publication type:
- Article
7
5 GHz all-digital delay-locked loop for future memory systems beyond double data rate 4 synchronous dynamic random access memory.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2015, v. 51, n. 24, p. 1973, doi. 10.1049/el.2015.2876
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- Publication type:
- Article
8
Wide-range harmonic lock detector with real-time delay measurement of delay-locked loop.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2015, v. 51, n. 2, p. 1, doi. 10.1049/el.2014.3749
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- Publication type:
- Article
9
All-digital PLL with ΔΣ DLL embedded TDC.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2013, v. 49, n. 2, p. 13
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- Publication type:
- Article
10
A Low-Jitter Fast-Locking Multi-phase Clock for High Resolution CCD Processor.
- Published in:
- IETE Journal of Research, 2015, v. 61, n. 3, p. 213, doi. 10.1080/03772063.2015.1009401
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- Publication type:
- Article
11
PREDICTING THE JITTER OF PLL-DLL BASED FREQUENCY SYNTHESIZERS.
- Published in:
- International Journal of Wavelets, Multiresolution & Information Processing, 2014, v. 12, n. 2, p. -1, doi. 10.1142/S0219691314500167
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- Publication type:
- Article
12
Analytical Models of Correlation Functions, DLL Discriminator Outputs and Multipath Envelope Errors for CosBOC(m, n) Modulated Signals in Coherent and Non-coherent Configurations.
- Published in:
- Wireless Personal Communications, 2015, v. 82, n. 2, p. 911, doi. 10.1007/s11277-014-2259-0
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- Publication type:
- Article
13
Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications.
- Published in:
- Sensors (14248220), 2016, v. 16, n. 10, p. 1593, doi. 10.3390/s16101593
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- Publication type:
- Article
14
Unique Micro System Stimulator with High Data Rate and Efficient Power Recovery Circuit.
- Published in:
- Przegląd Elektrotechniczny, 2016, v. 92, n. 11, p. 213, doi. 10.15199/48.2016.11.52
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- Publication type:
- Article
15
Compact and Broadband Variable True-Time Delay Line with DLL-Based Delay-Time Control.
- Published in:
- Circuits, Systems & Signal Processing, 2018, v. 37, n. 3, p. 1007, doi. 10.1007/s00034-017-0594-6
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- Publication type:
- Article
16
Analysis of DLL Jitter due to Voltage-Controlled Delay Line.
- Published in:
- Circuits, Systems & Signal Processing, 2013, v. 32, n. 5, p. 2119, doi. 10.1007/s00034-013-9584-5
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- Publication type:
- Article
17
A Novel Low Power Architecture for DLL-Based Frequency Synthesizers.
- Published in:
- Circuits, Systems & Signal Processing, 2013, v. 32, n. 2, p. 781, doi. 10.1007/s00034-012-9488-9
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- Publication type:
- Article
18
Contribution to Synchronization and Tracking Modelisation in a CDMA Receiver.
- Published in:
- Journal of Engineering (2314-4912), 2013, p. 1, doi. 10.1155/2013/936495
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- Publication type:
- Article
19
Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process.
- Published in:
- International Journal of Circuit Theory & Applications, 2017, v. 45, n. 6, p. 851, doi. 10.1002/cta.2267
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- Publication type:
- Article
20
A small fully digital open-loop clock and data recovery circuit for wired BANs.
- Published in:
- International Journal of Circuit Theory & Applications, 2016, v. 44, n. 3, p. 530, doi. 10.1002/cta.2092
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- Publication type:
- Article
21
A fast-corrected all-digital DCC with synchronous input clock.
- Published in:
- International Journal of Circuit Theory & Applications, 2015, v. 43, n. 12, p. 91, doi. 10.1002/cta.2042
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- Publication type:
- Article
22
A new fast-lock, low-jitter, and all-digital frequency synthesizer for DVB-T receivers.
- Published in:
- International Journal of Circuit Theory & Applications, 2015, v. 43, n. 5, p. 566, doi. 10.1002/cta.1958
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- Publication type:
- Article