Works matching DE "DATA pipelining"
Results: 76
Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration.
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- Journal of Information Science & Engineering, 2011, v. 27, n. 5, p. 1641
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- Article
Adaptive Continuous Collision Detection for Cloth Models Using a Skipping Frame Session.
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- Journal of Information Science & Engineering, 2011, v. 27, n. 5, p. 1545
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- Article
Multi-pipeline Processing Algorithm for Intensive Data Stream Processing of educational data using Soft Computing Techniques.
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- Journal of Positive School Psychology, 2022, v. 6, n. 3, p. 4601
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- Article
High Throughput FPGA Implementation of Data Encryption Standard with Time Variable Sub-Keys.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2016, v. 6, n. 1, p. 298, doi. 10.11591/ijece.v6i1.8388
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- Article
TLS: A Tabu Search Based Scheduling Algorithm for Behavioral Synthesis of Functional Pipelines.
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- Computer Journal, 2000, v. 43, n. 2, p. 152, doi. 10.1093/comjnl/43.2.152
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- Article
Resource-Directed Loop Pipelining: Exposing Just Enough Parallelism.
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- Computer Journal, 1997, v. 40, n. 6, p. 311, doi. 10.1093/comjnl/40.6.311
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- Article
Data Packet Processing Model based on Multi-Core Architecture.
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- International Journal of Performability Engineering, 2018, v. 14, n. 7, p. 1383, doi. 10.23940/ijpe.18.07.p1.13831390
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- Article
FPGA based Digital Filter Design for faster operations.
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- Journal of VLSI Circuits & Systems (JVCS), 2023, v. 5, n. 2, p. 56, doi. 10.31838/jvcs/05.02.09
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- Article
A PipelineTechnique for Dynamic Data Transfer on a Multiprocessor Grid.
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- International Journal of Parallel Programming, 2004, v. 32, n. 5, p. 361, doi. 10.1023/B:IJPP.0000038068.80639.52
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- Article
Dynamic Memory Instruction Bypassing.
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- International Journal of Parallel Programming, 2004, v. 32, n. 3, p. 199, doi. 10.1023/B:IJPP.0000029273.49634.19
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- Article
Loop Shifting for Loop Compaction.
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- International Journal of Parallel Programming, 2000, v. 28, n. 5, p. 499, doi. 10.1023/A:1007506711786
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- Article
Enhanced Co-Scheduling: A Software Pipelining Method Using Modulo-Scheduled Pipeline Theory.
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- International Journal of Parallel Programming, 2000, v. 28, n. 1, p. 1, doi. 10.1023/A:1007564126785
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- Article
Cloud-Based Infrastructure and DevOps for Energy Fault Detection in Smart Buildings.
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- Computers (2073-431X), 2024, v. 13, n. 1, p. 23, doi. 10.3390/computers13010023
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- Article
DUAL PRIORITY SCHEDULING ALGORITHM USED IN THE nMPRA MICROCONTROLLERS - DYNAMIC SCHEDULER.
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- Annals of the University Dunarea de Jos of Galati: Fascicle IX, Metallurgy & Materials Science, 2015, v. 33, n. 2, p. 66
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- Article
DETAILED MICROCONTROLLER ARCHITECTURE BASED ON A HARDWARE SCHEDULER ENGINE AND INDEPENDENT PIPELINE REGISTERS.
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- Annals of the University Dunarea de Jos of Galati: Fascicle IX, Metallurgy & Materials Science, 2015, v. 33, n. 1, p. 77
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- Article
Performance-Optimised Design of the RISC-V Five-Stage Pipelined Processor NRP.
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- International Journal of Advanced Computer Science & Applications, 2024, v. 15, n. 2, p. 276, doi. 10.14569/ijacsa.2024.0150229
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- Article
Hardware Implementation of 128-Bit AES Image Encryption with Low Power Techniques on FPGA.
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- Majlesi Journal of Electrical Engineering, 2012, v. 6, n. 4, p. 13
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- Article
Design and Implementation of Online Clock Skew Scheme-based Asynchronous Wave-pipelined Distributed Arithmetic Filters on FPGA.
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- IETE Journal of Research, 2012, v. 58, n. 6, p. 494, doi. 10.4103/0377-2063.106759
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- Article
A Simple Technique for Fast Digital Background Calibration of A/D Converters.
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- EURASIP Journal on Advances in Signal Processing, 2008, p. 1, doi. 10.1155/2008/453218
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- Article
Early Termination and Pipelining for Hardware Implementation of Fast H.264 Intraprediction Targeting Mobile HD Applications.
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- EURASIP Journal on Advances in Signal Processing, 2008, p. 1, doi. 10.1155/2008/542735
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- Article
WASP: a web-based simulator for an educational pipelined processor.
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- International Journal of Electrical Engineering Education, 2007, v. 44, n. 3, p. 197, doi. 10.7227/IJEEE.44.3.1
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- Article
Pipelined Architecture for Lossy Image Compression Using Hyper Analytic Wavelet.
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- International Review on Computers & Software, 2014, v. 9, n. 3, p. 427
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- Article
A Distributed Parallel Pipelined Hardware-Level Barrier Synchronization Method for Mesh-Connected Multicomputer.
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- International Review on Computers & Software, 2013, v. 8, n. 9, p. 2254
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- Article
Customized pipeline and instruction set architecture for embedded processing engines.
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- Journal of Supercomputing, 2014, v. 68, n. 2, p. 948, doi. 10.1007/s11227-013-1075-8
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- Article
Advances in Modern Information Technologies for Data Analysis in CRYO-EM and XFEL Experiments.
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- Crystallography Reports, 2020, v. 65, n. 6, p. 1081, doi. 10.1134/S1063774520060085
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- Article
Can All Sequential Processes Grow Up to Be Iterative and Incremental?
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- IEEE Software, 2010, v. 27, n. 4, p. 2, doi. 10.1109/MS.2010.94
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- Article
Fast Calculation Using Parallel Processing and Pipeline Processing in Power System Analysis.
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- Electrical Engineering in Japan, 1996, v. 116, n. 5, p. 85, doi. 10.1002/eej.4391160508
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- Article
Using SPDY to improve Web 2.0 over satellite links.
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- International Journal of Satellite Communications & Networking, 2017, v. 35, n. 4, p. 307, doi. 10.1002/sat.1185
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- Article
Clustered Communication for Efficient Pipelined Multithreading on Commodity MCPs.
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- IAENG International Journal of Computer Science, 2009, v. 36, n. 4, p. 275
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- Article
Recent Subthreshold Design Techniques.
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- Active & Passive Electronic Components, 2012, p. 1, doi. 10.1155/2012/926753
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- Article
Design and Implementation of Pipelining Based Area Efficient Fast Multiplier.
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- Journal of Active & Passive Electronic Devices, 2017, v. 12, n. 3/4/2017, p. 293
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- Article
Design and Implementation of Pipelining Based Area Efficient Fast Multiplier.
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- Journal of Active & Passive Electronic Devices, 2017, v. 12, n. 3/4, p. 293
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- Article
Developing and Testing High-Performance SHM Sensors Mounting Low-Noise MEMS Accelerometers.
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- Sensors (14248220), 2024, v. 24, n. 8, p. 2435, doi. 10.3390/s24082435
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- Article
Optimal pipeline stage balancing in the presence of large isolated interconnect delay.
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- Electronics Letters (Wiley-Blackwell), 2017, v. 53, n. 4, p. 229, doi. 10.1049/el.2016.4262
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- Article
Fast SVM-based epileptic seizure prediction employing data prefetching.
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- Electronics Letters (Wiley-Blackwell), 2013, v. 49, n. 1, p. 33, doi. 10.1049/el.2012.3414
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- Article
Investigation of the Stress-Strain State of Seamless Pipe in the Initial State.
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- Archive of Mechanical Engineering, 2014, v. 61, n. 4, p. 595, doi. 10.2478/meceng-2014-0034
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- Article
Toward a modular and efficient distribution for Web service handlers.
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- Concurrency & Computation: Practice & Experience, 2013, v. 25, n. 3, p. 410, doi. 10.1002/cpe.2854
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- Article
Towards the optimal synchronization granularity for dynamic scheduling of pipelined computations on heterogeneous computing systems.
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- Concurrency & Computation: Practice & Experience, 2012, v. 24, n. 18, p. 2302, doi. 10.1002/cpe.2812
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- Article
Special issue: advanced topics on scalable computing.
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- Concurrency & Computation: Practice & Experience, 2010, v. 22, n. 13, p. 1849, doi. 10.1002/cpe.1653
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- Article
I/O scheduling and performance analysis on multi-core platforms.
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- Concurrency & Computation: Practice & Experience, 2009, v. 21, n. 10, p. 1405, doi. 10.1002/cpe.1421
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- Article
OPS: Opportunistic pipeline scheduling in long-strip wireless sensor networks with unreliable links.
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- Wireless Networks (10220038), 2015, v. 21, n. 5, p. 1669, doi. 10.1007/s11276-014-0807-x
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- Article
A VIDEO ENHANCEMENT ALGORITHM FOR LOW-LIGHTING ENVIRONMENT USING FIELD PROGRAMMABLE GATE ARRAY (FPGA) ARCHITECTURE.
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- NED University Journal of Research, 2016, v. 13, n. 4, p. 81
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- Article
Pipelined-Scheduling of Multiple Embedded Applications on a Multi-Processor-SoC.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 3, p. -1, doi. 10.1142/S0218126617500426
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- Article
NOVEL PIPELINED INTERPOLATOR FOR REED-SOLOMON DECODER BASED ON LOW-COMPLEXITY CHASE DECODING.
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- Journal of Circuits, Systems & Computers, 2013, v. 22, n. 10, p. 1, doi. 10.1142/S0218126613400379
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- Article
A 3.1 GB/s, 8 Kb, ZERO PRECHARGE, PIPELINED, HIGHLY STABLE 2-PORT 8T SRAM DESIGN IN 65 nm.
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- Journal of Circuits, Systems & Computers, 2013, v. 22, n. 8, p. -1, doi. 10.1142/S0218126613500692
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- Article
SPINTRONIC DEVICES AND CIRCUITS FOR LOW-VOLTAGE LOGIC.
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- International Journal of High Speed Electronics & Systems, 2012, v. 21, n. 1, p. -1, doi. 10.1142/S012915641250005X
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- Article
OPTIMIZATION OF OPERATING PARAMETERS USING RESPONSE SURFACE METHODOLOGY FOR PARAFFIN-WAX DEPOSITION IN PIPELINE.
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- Petroleum & Coal, 2014, v. 56, n. 1, p. 19
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- Publication type:
- Article
PSReliP: an integrated pipeline for analysis and visualization of population structure and relatedness based on genome-wide genetic variant data.
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- BMC Bioinformatics, 2023, v. 24, n. 1, p. 1, doi. 10.1186/s12859-023-05169-4
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- Article
Minimal Unroll Factor for Code Generation of Software Pipelining.
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- International Journal of Parallel Programming, 2013, v. 41, n. 1, p. 1, doi. 10.1007/s10766-012-0203-z
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- Article
LALP: A Language to Program Custom FPGA-Based Acceleration Engines.
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- International Journal of Parallel Programming, 2012, v. 40, n. 3, p. 262, doi. 10.1007/s10766-011-0187-0
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- Article