Works matching DE "DATA pipelining"

Results: 77

Performance-Optimised Design of the RISC-V Five-Stage Pipelined Processor NRP.

Published in:

International Journal of Advanced Computer Science & Applications, 2024, v. 15, n. 2, p. 276, doi. 10.14569/ijacsa.2024.0150229

By:

Hongkui Li;
Chaoxia Jing;
Jie Liu

Publication type:

Article

The MC-Fold and MC-Sym pipeline infers RNA structure from sequence data.

Published in:

Nature, 2008, v. 452, n. 7183, p. 51, doi. 10.1038/nature06684

By:

Parisien, Marc;
Major, François

Publication type:

Article

Comprehensive Review and Comparative Analysis of Hardware Architectures for Sobel Edge Detector.

Published in:

ISRN Otolaryngology, 2014, p. 1, doi. 10.1155/2014/857912

By:

Singh, Sanjay;
Saurav, Sumeet;
Saini, Ravi;
Saini, Anil Kumar;
Shekhar, Chandra;
Vohra, Anil

Publication type:

Article

Hardware Implementation of 128-Bit AES Image Encryption with Low Power Techniques on FPGA.

Published in:

Majlesi Journal of Electrical Engineering, 2012, v. 6, n. 4, p. 13

By:

Farmani, Ali;
Bahar, Hossein Balazadeh

Publication type:

Article

Design and Implementation of Pipelining Based Area Efficient Fast Multiplier.

Published in:

Journal of Active & Passive Electronic Devices, 2017, v. 12, n. 3/4/2017, p. 293

By:

Jain, Ruby;
Jain, Vivek

Publication type:

Article

Design and Implementation of Pipelining Based Area Efficient Fast Multiplier.

Published in:

Journal of Active & Passive Electronic Devices, 2017, v. 12, n. 3/4, p. 293

By:

JAIN, RUBY;
JAIN, VIVEK

Publication type:

Article

CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator.

Published in:

Journal of Electronic Testing, 2016, v. 32, n. 5, p. 625, doi. 10.1007/s10836-016-5615-z

By:

Yeh, Kuen-Wei;
Huang, Jiun-Lang;
Wang, Laung-Terng

Publication type:

Article

Tracing and using data lineage for pipeline processing in Astro-WISE.

Published in:

Experimental Astronomy, 2013, v. 35, n. 1/2, p. 131, doi. 10.1007/s10686-011-9276-8

By:

Mwebaze, Johnson;
Boxhoorn, Danny;
Valentijn, Edwin

Publication type:

Article

Advances in Modern Information Technologies for Data Analysis in CRYO-EM and XFEL Experiments.

Published in:

Crystallography Reports, 2020, v. 65, n. 6, p. 1081, doi. 10.1134/S1063774520060085

By:

Bobkov, S. A.;
Teslyuk, A. B.;
Baymukhametov, T. N.;
Pichkur, E. B.;
Chesnokov, Yu. M.;
Assalauova, D.;
Poyda, A. A.;
Novikov, A. M.;
Zolotarev, S. I.;
Ikonnikova, K. A.;
Velikhov, V. E.;
Vartanyants, I. A.;
Vasiliev, A. L.;
Ilyin, V. A.

Publication type:

Article

Minimal Unroll Factor for Code Generation of Software Pipelining.

Published in:

International Journal of Parallel Programming, 2013, v. 41, n. 1, p. 1, doi. 10.1007/s10766-012-0203-z

By:

Bachir, Mounira;
Touati, Sid-Ahmed-Ali;
Brault, Frederic;
Gregg, David;
Cohen, Albert

Publication type:

Article

LALP: A Language to Program Custom FPGA-Based Acceleration Engines.

Published in:

International Journal of Parallel Programming, 2012, v. 40, n. 3, p. 262, doi. 10.1007/s10766-011-0187-0

By:

Menotti, Ricardo;
Cardoso, João;
Fernandes, Marcio;
Marques, Eduardo

Publication type:

Article

Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors.

Published in:

International Journal of Parallel Programming, 2008, v. 36, n. 2, p. 267, doi. 10.1007/s10766-007-0063-0

By:

Loh, Gabriel;
Jiménez, Daniel

Publication type:

Article

The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor.

Published in:

International Journal of Parallel Programming, 2007, v. 35, n. 3, p. 233, doi. 10.1007/s10766-007-0035-4

By:

Gschwind, Michael

Publication type:

Article

A PipelineTechnique for Dynamic Data Transfer on a Multiprocessor Grid.

Published in:

International Journal of Parallel Programming, 2004, v. 32, n. 5, p. 361, doi. 10.1023/B:IJPP.0000038068.80639.52

By:

Souravlas, Stavros;
Roumeliotis, Manos

Publication type:

Article

Dynamic Memory Instruction Bypassing.

Published in:

International Journal of Parallel Programming, 2004, v. 32, n. 3, p. 199, doi. 10.1023/B:IJPP.0000029273.49634.19

By:

Ortega, Daniel;
Valero, Mateo;
Ayguadé, Eduard

Publication type:

Article

Loop Shifting for Loop Compaction.

Published in:

International Journal of Parallel Programming, 2000, v. 28, n. 5, p. 499, doi. 10.1023/A:1007506711786

By:

Darte, Alain;
Huard, Guillaume

Publication type:

Article

Enhanced Co-Scheduling: A Software Pipelining Method Using Modulo-Scheduled Pipeline Theory.

Published in:

International Journal of Parallel Programming, 2000, v. 28, n. 1, p. 1, doi. 10.1023/A:1007564126785

By:

Govindarajan, R.;
Rao, N. S. S. Narasimha;
Altman, E. R.;
Gao, Guang R.

Publication type:

Article

OPS: Opportunistic pipeline scheduling in long-strip wireless sensor networks with unreliable links.

Published in:

Wireless Networks (10220038), 2015, v. 21, n. 5, p. 1669, doi. 10.1007/s11276-014-0807-x

By:

Guo, Peng;
Meratnia, Nirvana;
Havinga, Paul;
Jiang, Hongbo;
Zhang, Kui

Publication type:

Article

DUAL PRIORITY SCHEDULING ALGORITHM USED IN THE nMPRA MICROCONTROLLERS - DYNAMIC SCHEDULER.

Published in:

Annals of the University Dunarea de Jos of Galati: Fascicle IX, Metallurgy & Materials Science, 2015, v. 33, n. 2, p. 66

By:

ANDRIEȘ, Lucian;
GĂITAN, Vasile Gheorghiță

Publication type:

Article

DETAILED MICROCONTROLLER ARCHITECTURE BASED ON A HARDWARE SCHEDULER ENGINE AND INDEPENDENT PIPELINE REGISTERS.

Published in:

Annals of the University Dunarea de Jos of Galati: Fascicle IX, Metallurgy & Materials Science, 2015, v. 33, n. 1, p. 77

By:

ANDRIES, Lucian;
GAITAN, Vasile Gheorghita

Publication type:

Article

Pipelined-Scheduling of Multiple Embedded Applications on a Multi-Processor-SoC.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 3, p. -1, doi. 10.1142/S0218126617500426

By:

Salamy, Hassan;
Aslan, Semih

Publication type:

Article

NOVEL PIPELINED INTERPOLATOR FOR REED-SOLOMON DECODER BASED ON LOW-COMPLEXITY CHASE DECODING.

Published in:

Journal of Circuits, Systems & Computers, 2013, v. 22, n. 10, p. 1, doi. 10.1142/S0218126613400379

By:

HAO WANG;
WEI ZHANG;
YANYAN LIU

Publication type:

Article

A 3.1 GB/s, 8 Kb, ZERO PRECHARGE, PIPELINED, HIGHLY STABLE 2-PORT 8T SRAM DESIGN IN 65 nm.

Published in:

Journal of Circuits, Systems & Computers, 2013, v. 22, n. 8, p. -1, doi. 10.1142/S0218126613500692

By:

SIL, ABHIJIT;
BALUSU, KRISHNA PRASAD;
GURRAM, CHANDRA SEKHAR;
BAYOUMI, MAGDY

Publication type:

Article

Seamless Pipelining of DSP Circuits.

Published in:

Circuits, Systems & Signal Processing, 2016, v. 35, n. 4, p. 1147, doi. 10.1007/s00034-015-0089-2

By:

Meher, Pramod

Publication type:

Article

An Improved Direct Digital Synthesizer Using Hybrid Wave Pipelining and CORDIC algorithm for Software Defined Radio.

Published in:

Circuits, Systems & Signal Processing, 2013, v. 32, n. 3, p. 1219, doi. 10.1007/s00034-012-9495-x

By:

Madheswaran, M.;
Menakadevi, T.

Publication type:

Article

Adaptive Continuous Collision Detection for Cloth Models Using a Skipping Frame Session.

Published in:

Journal of Information Science & Engineering, 2011, v. 27, n. 5, p. 1545

By:

SAI-KEUNG WONG

Publication type:

Article

Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration.

Published in:

Journal of Information Science & Engineering, 2011, v. 27, n. 5, p. 1641

By:

I-WEI WU;
CHUNG-PING CHUNG;
SHANN, JEAN JYH-JIUN

Publication type:

Article

High-throughput implementation of lifting-based discrete wavelet transforms using look-ahead pipelining.

Published in:

Optical Engineering, 2010, v. 49, n. 10, p. 107003

By:

Zhirong Gao;
Chengyi Xiong

Publication type:

Article

Toward a modular and efficient distribution for Web service handlers.

Published in:

Concurrency & Computation: Practice & Experience, 2013, v. 25, n. 3, p. 410, doi. 10.1002/cpe.2854

By:

Yildiz, Beytullah;
Fox, Geoffrey C.

Publication type:

Article

Towards the optimal synchronization granularity for dynamic scheduling of pipelined computations on heterogeneous computing systems.

Published in:

Concurrency & Computation: Practice & Experience, 2012, v. 24, n. 18, p. 2302, doi. 10.1002/cpe.2812

By:

Riakiotakis, I.;
Ciorba, F. M.;
Andronikos, T.;
Papakonstantinou, G.;
Chronopoulos, A. T.

Publication type:

Article

Special issue: advanced topics on scalable computing.

Published in:

Concurrency & Computation: Practice & Experience, 2010, v. 22, n. 13, p. 1849, doi. 10.1002/cpe.1653

By:

Wenyu Qu;
Zhaobin Liu;
Kai Lin

Publication type:

Article

I/O scheduling and performance analysis on multi-core platforms.

Published in:

Concurrency & Computation: Practice & Experience, 2009, v. 21, n. 10, p. 1405, doi. 10.1002/cpe.1421

By:

Zhaobin Liu;
Wenyu Qu;
Haitao Li;
Min Ruan;
Wanlei Zhou

Publication type:

Article

Accelerating Dynamic Programming by P-Fold Pipeline Implementation on GPU.

Published in:

International Journal for Computers & Their Applications, 2023, v. 30, n. 2, p. 121

By:

Matsumae, Susumu

Publication type:

Article

An Adaptable Memory System Using Reconfigurable Row DRAM To Improve Performance Of Multi Core For Big Data.

Published in:

International Journal for Computers & Their Applications, 2021, v. 28, n. 2, p. 84

By:

Mekhiel, Nagi

Publication type:

Article

Using SPDY to improve Web 2.0 over satellite links.

Published in:

International Journal of Satellite Communications & Networking, 2017, v. 35, n. 4, p. 307, doi. 10.1002/sat.1185

By:

Cardaci, Andrea;
Caviglione, Luca;
Ferro, Erina;
Gotta, Alberto

Publication type:

Article

The Effect of Dependency on Scalar Pipeline Architecture.

Published in:

IUP Journal of Computer Sciences, 2017, v. 11, n. 1, p. 38

By:

Patel, Renuka;
Kumar, Sanjay

Publication type:

Article

SPINTRONIC DEVICES AND CIRCUITS FOR LOW-VOLTAGE LOGIC.

Published in:

International Journal of High Speed Electronics & Systems, 2012, v. 21, n. 1, p. -1, doi. 10.1142/S012915641250005X

By:

MORRIS, DANIEL H.;
BROMBERG, DAVID M.;
ZHU, JIAN-GANG (JIMMY);
PILEGGI, LARRY

Publication type:

Article

Past, Present, and Future Thoughts on Immersive Visualization Laboratories Through the Story of the Wisconsin Institute for Discovery Virtual Environments Group.

Published in:

PRESENCE: Virtual & Augmented Reality, 2024, v. 33, p. 1, doi. 10.1162/pres_a_00411

By:

Tredinnick, Ross;
Schloss, Karen;
Ponto, Kevin

Publication type:

Article

Combined High-Throughput Imaging and Sequencing: Addressing the collections on demand requirement in SYNTHESYS+ project.

Published in:

2019

By:

Arvanitidis, Christos;
Hollingsworth, Peter;
Mergen, Patricia;
Semal, Patrick;
Keklikoglou, Kleoniki;
Chatzinikolaou, Eva;
Addnik, Wouter;
Smith, Vincent;
Koureas, Dimitrios

Publication type:

Abstract

Integration, Attribution, and Value in the Web of Natural History Museum Data.

Published in:

2018

By:

Bentley, Andrew

Publication type:

Abstract

Establishment of the ARCTOS-GGBN Data Pipeline.

Published in:

2018

By:

Mayfield, Teresa Jegelewicz;
Campbell, Mariel;
Hildebrandt, Kyndall;
Cicero, Carla;
McDonald, Dusty;
Cook, Joseph;
Demboski, John

Publication type:

Abstract

Completing the Data Pipeline: Collections Data Use in Research, Education and Outreach.

Published in:

2018

By:

Nelson, Gil;
Phillips, Molly;
Monfils, Anna;
MacFadden, Bruce;
Hogue, Gabriela

Publication type:

Abstract

PIPELINED ARCHITECTURES FOR TRANSFORM DOMAIN LMS ADAPTIVE FILTERING.

Published in:

Journal of Circuits, Systems & Computers, 2005, v. 14, n. 3, p. 553, doi. 10.1142/S0218126605002519

By:

George-Othon Glentis

Publication type:

Article

WASP: a web-based simulator for an educational pipelined processor.

Published in:

International Journal of Electrical Engineering Education, 2007, v. 44, n. 3, p. 197, doi. 10.7227/IJEEE.44.3.1

By:

Stojkovic, A.;
Djordjevic, J.;
Nikolic, B.

Publication type:

Article

Data as an essential facility in European law: how to define the "target" market and divert the data pipeline?

Published in:

European Competition Journal, 2019, v. 15, n. 2/3, p. 177, doi. 10.1080/17441056.2019.1644576

By:

Bruc, Édouard

Publication type:

Article

Software pipelining for graphic processing unit acceleration: Partition, scheduling and granularity.

Published in:

International Journal of High Performance Computing Applications, 2016, v. 30, n. 2, p. 169, doi. 10.1177/1094342015585845

By:

Liu, Bozhong;
Qiu, Weidong;
Jiang, Lin;
Gong, Zheng

Publication type:

Article

Pipelined Architecture for Lossy Image Compression Using Hyper Analytic Wavelet.

Published in:

International Review on Computers & Software, 2014, v. 9, n. 3, p. 427

By:

N., Abdul Jaleel;
Vijayakumar, P.

Publication type:

Article

A Distributed Parallel Pipelined Hardware-Level Barrier Synchronization Method for Mesh-Connected Multicomputer.

Published in:

International Review on Computers & Software, 2013, v. 8, n. 9, p. 2254

By:

Zotov, Igor V.;
Bredikhin, Ruslan V.;
Titenko, Evgeni A.

Publication type:

Article

Recent Subthreshold Design Techniques.

Published in:

Active & Passive Electronic Components, 2012, p. 1, doi. 10.1155/2012/926753

By:

Radfar, Mohsen;
Shah, Kriyang;
Singh, Jugdutt

Publication type:

Article

Can All Sequential Processes Grow Up to Be Iterative and Incremental?

Published in:

IEEE Software, 2010, v. 27, n. 4, p. 2, doi. 10.1109/MS.2010.94

By:

Erdogmus, Hakan

Publication type:

Article