Benefits of Partitioning in a Projection-based and Realizable Model-order Reduction Flow.
- Published in:
- Journal of Electronic Testing, 2014, v. 30, n. 3, p. 271, doi. 10.1007/s10836-014-5451-y
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- Publication type:
- Article
Works matching DE "COMPUTER simulation of electronic circuits"
Results: 14
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High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design.
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- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 537, doi. 10.1007/s10836-013-5384-x
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- Article
3
Incorporating feedforward action into self-optimising control policies.
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- Canadian Journal of Chemical Engineering, 2014, v. 92, n. 1, p. 90, doi. 10.1002/cjce.21783
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- Article
4
Optimal Switching Characterization of High Speed CMOS Inverter Design Using Social Emotional Optimization Algorithm.
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- Journal of Engineering Science & Technology Review, 2018, v. 11, n. 2, p. 182, doi. 10.25103/jestr.112.24
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- Article
5
Second-order charge-sampling structure utilising passive scheme to implement complex conjugate poles.
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- Electronics Letters (Wiley-Blackwell), 2016, v. 52, n. 12, p. 1015, doi. 10.1049/el.2016.0668
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- Article
6
LUT-oriented dual-rail quasi-delay-insensitive logic synthesis.
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- Electronics Letters (Wiley-Blackwell), 2014, v. 50, n. 7, p. 1, doi. 10.1049/el.2014.0242
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- Article
7
Analogue circuit design methodology using self-cascode structures.
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- Electronics Letters (Wiley-Blackwell), 2013, v. 49, n. 9, p. 1, doi. 10.1049/el.2013.0554
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- Article
8
Analysis Simulation & Hardware Designing of Digital Systems.
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- International Transactions in Applied Sciences, 2011, v. 3, n. 3, p. 381
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- Article
9
Delay model for dynamically switching coupled RLC interconnects.
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- European Physical Journal - Applied Physics, 2014, v. 66, n. 1, p. 00, doi. 10.1051/epjap/2014130375
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- Article
10
Application of the Averaged Model of the Diode-transistor Switch for Modelling Characteristics of a Boost Converter with an IGBT.
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- International Journal of Electronics & Telecommunications, 2020, v. 66, n. 3, p. 535, doi. 10.24425/ijet.2020.134012
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- Article
11
Analysis of earth faults in the MV grid using the EMTP-ATP program.
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- Przegląd Elektrotechniczny, 2019, v. 95, n. 2, p. 146, doi. 10.15199/48.2019.02.32
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- Article
12
Modelling of BLDC motor with different fashions of winding connection.
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- Przegląd Elektrotechniczny, 2019, v. 95, n. 2, p. 92, doi. 10.15199/48.2019.02.21
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- Article
13
A Unified Delay, Power and Crosstalk Model for Current Mode Signaling Multiwall Carbon Nanotube Interconnects.
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- Circuits, Systems & Signal Processing, 2018, v. 37, n. 4, p. 1359, doi. 10.1007/s00034-017-0614-6
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- Article
14
Gramian-based model order reduction of parameterized time-delay systems.
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- International Journal of Circuit Theory & Applications, 2014, v. 42, n. 7, p. 687, doi. 10.1002/cta.1884
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- Article