Works matching DE "COMPUTER arithmetic %26 logic units"

Results: 31

Elixent adds routing to tackle control in signal processing.

Published in:: Electronics Systems & Software, 2005, v. 3, n. 3, p. 47
Publication type:: Article

Design and Implementation of a 32-Bit ALU: A Review.

Published in:

IUP Journal of Telecommunications, 2019, v. 11, n. 1, p. 53

By:

Nandan, Hari;
Dahiya, Pawan Kumar

Publication type:

Article

MANIFEST ZUR BILDUNG EINER MATRIX [CODE], SICHERUNG UND VERSCHLEISS DES CULTURAL HERITAGE IN EUROPA.

Published in:

Mitteilungen der Vereinigung Österreichischer Bibliothekarinnen & Bibliothekare, 2010, v. 63, n. 1/2, p. 16

By:

Budroni, Paolo

Publication type:

Article

An Independence Result for Intuitionistic Bounded Arithmetic.

Published in:

Journal of Logic & Computation, 2006, v. 16, n. 2, p. 199, doi. 10.1093/logcom/exi085

By:

Moniri, Morteza

Publication type:

Article

Optimization Approaches for Designing Quantum Reversible Arithmetic Logic Unit.

Published in:

International Journal of Theoretical Physics, 2016, v. 55, n. 3, p. 1423, doi. 10.1007/s10773-015-2782-0

By:

Haghparast, Majid;
Bolhassani, Ali

Publication type:

Article

Multilayer four-way power divider with improved isolation performance.

Published in:

Journal of Electromagnetic Waves & Applications, 2017, v. 31, n. 16, p. 1676, doi. 10.1080/09205071.2017.1359684

By:

Hu, Shunyong;
Song, Kaijun;
Fan, Yong

Publication type:

Article

WHEN CHURCH-ROSSER BECOMES CONTEXT FREE.

Published in:

International Journal of Foundations of Computer Science, 2007, v. 18, n. 6, p. 1293, doi. 10.1142/S0129054107005339

By:

KUTRIB, MARTIN;
MALCHER, ANDREAS;
Stiebe, R.

Publication type:

Article

8-bit AVR Microcontroller with 2K Bytes In-System Programmable Flash.

Published in:: Radioengineering, 2011, v. 20, n. 4, p. 1
Publication type:: Article

Circuits arithm?tiques et calculs tensoriels.

Published in:: Journal of the Institute of Mathematics of Jussieu, 2008, v. 7, n. 4, p. 869, doi. 10.1017/S1474748008000248
Publication type:: Article

Evaluation of two W-band power dividers in a subwavelength dielectric fibre technology.

Published in:

Electronics Letters (Wiley-Blackwell), 2016, v. 52, n. 16, p. 1391, doi. 10.1049/el.2016.1092

By:

Reese, R.;
Jost, M.;
Jakoby, R.

Publication type:

Article

Forwarding Path Limitation and Instruction Allocation for In-Order Processor with ALU Cascading.

Published in:

Journal of Low Power Electronics & Applications, 2017, v. 7, n. 4, p. 32, doi. 10.3390/jlpea7040032

By:

Ryotaro Kobayashi;
Anri Suzuki;
Hajime Shimada

Publication type:

Article

AN EFFICIENT REVERSE CONVERTER FOR THE NEW FOUR-MODULI SET {22n, 2n+1 - 1, 2n/2 + 1, 2n/2 - 1}.

Published in:

Journal of Circuits, Systems & Computers, 2011, v. 20, n. 7, p. 1341, doi. 10.1142/S0218126611007906

By:

NOORIMEHR, MOHAMMADREZA;
HOSSEINZADEH, MEHDI;
FARSHIDI, REZA

Publication type:

Article

HARDWARE IMPLEMENTATION AND VERIFICATION OF FIR FILTER UTILIZING M-BIT PDA.

Published in:

Journal of Circuits, Systems & Computers, 2010, v. 19, n. 2, p. 503, doi. 10.1142/S0218126610006207

By:

JENG, SHIANN-SHIUN;
LIN, HSING-CHEN;
CHEN, CHUN-CHYUAN;
CHANG, SHU-MING

Publication type:

Article

DESIGN OF LOW POWER 14T FULL ADDER CELL USING DOUBLE GATE MOSFET WITH MTCMOS REDUCTION TECHNIQUE AT 45 NANOMETER TECHNOLOGY.

Published in:

International Journal of Nanoscience, 2013, v. 12, n. 6, p. -1, doi. 10.1142/S0219581X13500427

By:

SHRIVASTAVA, ANUJ KUMAR;
AKASHE, SHYAM

Publication type:

Article

Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization.

Published in:

Wireless Personal Communications, 2018, v. 98, n. 4, p. 3549, doi. 10.1007/s11277-017-5028-z

By:

Tomar, Geetam Singh;
George, Marcus Lloyde

Publication type:

Article

Analysis of Low Power Consumption Techniques on FPGA for Wireless Devices.

Published in:

Wireless Personal Communications, 2017, v. 95, n. 2, p. 353, doi. 10.1007/s11277-016-3896-2

By:

Verma, Gaurav;
Kumar, Manish;
Khare, Vijay;
Pandey, Bishwajeet

Publication type:

Article

Design of U-Shaped In-Phase Power Divider Employing Ground-Slotted Technique for Wideband Applications.

Published in:

Wireless Personal Communications, 2015, v. 81, n. 1, p. 359, doi. 10.1007/s11277-014-2133-0

By:

Yusof, Khairul;
Seman, Norhudah;
Jamaluddin, Mohd

Publication type:

Article

Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA.

Published in:

Wireless Personal Communications, 2014, v. 76, n. 3, p. 569, doi. 10.1007/s11277-014-1725-z

By:

Kumar, Tanesh;
Pandey, Bishwajeet;
Das, Teerath;
Chowdhry, B.

Publication type:

Article

On Nearest-Neighbor Error-Correcting Output Codes with Application to All-Pairs Multiclass Support Vector Machines.

Published in:

Journal of Machine Learning Research, 2004, v. 4, n. 1, p. 1, doi. 10.1162/153244304322765612

By:

Klautau, Aldebaro;
Jevtić, Nikola;
Orlitsky, Alon

Publication type:

Article

A NOVEL MULTI-WAY POWER DIVIDER DESIGN WITH ARBITRARY COMPLEX TERMINATED IMPEDANCES.

Published in:

Progress in Electromagnetics Research B, 2013, v. 53, p. 315, doi. 10.2528/pierb13061306

By:

Jiuchao Li;
Yuanan Liu;
Shulan Li;
Cuiping Yu;
Yongle Wu;
Ming Su

Publication type:

Article

PARALLELIZATION OF REVERSIBLE RIPPLE-CARRY ADDERS.

Published in:

Parallel Processing Letters, 2009, v. 19, n. 2, p. 205, doi. 10.1142/S0129626409000171

By:

THOMSEN, MICHAEL KIRKEDAL;
AXELSEN, HOLGER BOCK

Publication type:

Article

Low Power Delay Product 8-bit ALU Design using Decoder and Data Selector.

Published in:

Majlesi Journal of Electrical Engineering, 2018, v. 12, n. 1, p. 103

By:

Telagam, Nagarjuna;
Kandasamy, Nehru

Publication type:

Article

BZK.SAU.FPGA10.1: A modular approach to FPGA-based micro computer architecture design for educational purpose.

Published in:

Computer Applications in Engineering Education, 2014, v. 22, n. 2, p. 272, doi. 10.1002/cae.20553

By:

Oztekin, Halit;
Temurtas, Feyzullah;
Gulbag, Ali

Publication type:

Article

Optimized designs of reversible arithmetic logic unit.

Published in:

Turkish Journal of Electrical Engineering & Computer Sciences, 2017, v. 25, n. 2, p. 1137, doi. 10.3906/elk-1505-223

By:

BOLHASSANI, Ali;
HAGHPARAST, Majid

Publication type:

Article

CMOS Technology for Increasing Efficiency of Clock Gating Techniques Using Tri-State Buffer.

Published in:

Walailak Journal of Science & Technology, 2017, v. 14, n. 4, p. 327

By:

HAMEED, Maan;
KHMAG, Asem;
ZAMAN, Fakhrul;
RAMLI, Abdurrahman

Publication type:

Article

CORDIC: Elementary Function Computation Using Recursive Sequences.

Published in:

College Mathematics Journal, 2001, v. 32, n. 5, p. 330, doi. 10.2307/2687303

By:

Eklund, Neil

Publication type:

Article

Declarative Infrastructure Configuration Synthesis and Debugging.

Published in:

Journal of Network & Systems Management, 2008, v. 16, n. 3, p. 235, doi. 10.1007/s10922-008-9108-y

By:

Narain, Sanjai;
Levin, Gary;
Malik, Sharad;
Kaul, Vikram

Publication type:

Article

Algebraic Characterization of Reversible Logic Gates.

Published in:

Theory of Computing Systems, 2006, v. 39, n. 2, p. 311, doi. 10.1007/s00224-004-1166-2

By:

Xiaoyu Song;
Guowu Yang;
Perkowski, Marek;
Yuke Wang

Publication type:

Article

Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error Cancelation.

Published in:

Circuits, Systems & Signal Processing, 2017, v. 36, n. 11, p. 4309, doi. 10.1007/s00034-017-0534-5

By:

Chang, Ik;
Park, Sang;
Choi, Jun

Publication type:

Article

Toward theoretical synthesis of biocomputer.

Published in:

IET Systems Biology (Wiley-Blackwell), 2017, v. 11, n. 1, p. 36, doi. 10.1049/iet-syb.2016.0015

By:

Ting-Yu Kuo;
Chun-Liang Lin;
Charoenkit, Natdanai;
Yang-Yi Chen;
Preuksakarn, Chakkrit

Publication type:

Article

A Fast ALU Design in CMOS for Low Voltage Operation.

Published in:

VLSI Design, 2002, v. 14, n. 4, p. 315, doi. 10.1080/10655140290011122

By:

Srivastava, A.;
Govindarajan, D.

Publication type:

Article