Works matching DE "COMPUTER arithmetic %26 logic units"
Results: 30
Optimized designs of reversible arithmetic logic unit.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2017, v. 25, n. 2, p. 1137, doi. 10.3906/elk-1505-223
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CMOS Technology for Increasing Efficiency of Clock Gating Techniques Using Tri-State Buffer.
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- Walailak Journal of Science & Technology, 2017, v. 14, n. 4, p. 327
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- Article
Low Power Delay Product 8-bit ALU Design using Decoder and Data Selector.
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- Majlesi Journal of Electrical Engineering, 2018, v. 12, n. 1, p. 103
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8-bit AVR Microcontroller with 2K Bytes In-System Programmable Flash.
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- Radioengineering, 2011, v. 20, n. 4, p. 1
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- Article
A Fast ALU Design in CMOS for Low Voltage Operation.
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- VLSI Design, 2002, v. 14, n. 4, p. 315, doi. 10.1080/10655140290011122
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On Nearest-Neighbor Error-Correcting Output Codes with Application to All-Pairs Multiclass Support Vector Machines.
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- Journal of Machine Learning Research, 2004, v. 4, n. 1, p. 1, doi. 10.1162/153244304322765612
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- Article
Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error Cancelation.
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- Circuits, Systems & Signal Processing, 2017, v. 36, n. 11, p. 4309, doi. 10.1007/s00034-017-0534-5
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- Article
BZK.SAU.FPGA10.1: A modular approach to FPGA-based micro computer architecture design for educational purpose.
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- Computer Applications in Engineering Education, 2014, v. 22, n. 2, p. 272, doi. 10.1002/cae.20553
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Toward theoretical synthesis of biocomputer.
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- IET Systems Biology (Wiley-Blackwell), 2017, v. 11, n. 1, p. 36, doi. 10.1049/iet-syb.2016.0015
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- Article
Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization.
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- Wireless Personal Communications, 2018, v. 98, n. 4, p. 3549, doi. 10.1007/s11277-017-5028-z
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A NOVEL MULTI-WAY POWER DIVIDER DESIGN WITH ARBITRARY COMPLEX TERMINATED IMPEDANCES.
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- Progress in Electromagnetics Research B, 2013, v. 53, p. 315, doi. 10.2528/pierb13061306
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PARALLELIZATION OF REVERSIBLE RIPPLE-CARRY ADDERS.
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- Parallel Processing Letters, 2009, v. 19, n. 2, p. 205, doi. 10.1142/S0129626409000171
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- Article
WHEN CHURCH-ROSSER BECOMES CONTEXT FREE.
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- International Journal of Foundations of Computer Science, 2007, v. 18, n. 6, p. 1293, doi. 10.1142/S0129054107005339
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Evaluation of two W-band power dividers in a subwavelength dielectric fibre technology.
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- Electronics Letters (Wiley-Blackwell), 2016, v. 52, n. 16, p. 1391, doi. 10.1049/el.2016.1092
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- Article
Multilayer four-way power divider with improved isolation performance.
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- Journal of Electromagnetic Waves & Applications, 2017, v. 31, n. 16, p. 1676, doi. 10.1080/09205071.2017.1359684
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- Article
Optimization Approaches for Designing Quantum Reversible Arithmetic Logic Unit.
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- International Journal of Theoretical Physics, 2016, v. 55, n. 3, p. 1423, doi. 10.1007/s10773-015-2782-0
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Design and Implementation of a 32-Bit ALU: A Review.
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- IUP Journal of Telecommunications, 2019, v. 11, n. 1, p. 53
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Elixent adds routing to tackle control in signal processing.
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- Electronics Systems & Software, 2005, v. 3, n. 3, p. 47
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Forwarding Path Limitation and Instruction Allocation for In-Order Processor with ALU Cascading.
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- Journal of Low Power Electronics & Applications, 2017, v. 7, n. 4, p. 32, doi. 10.3390/jlpea7040032
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An Independence Result for Intuitionistic Bounded Arithmetic.
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- Journal of Logic & Computation, 2006, v. 16, n. 2, p. 199, doi. 10.1093/logcom/exi085
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Declarative Infrastructure Configuration Synthesis and Debugging.
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- Journal of Network & Systems Management, 2008, v. 16, n. 3, p. 235, doi. 10.1007/s10922-008-9108-y
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DESIGN OF LOW POWER 14T FULL ADDER CELL USING DOUBLE GATE MOSFET WITH MTCMOS REDUCTION TECHNIQUE AT 45 NANOMETER TECHNOLOGY.
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- International Journal of Nanoscience, 2013, v. 12, n. 6, p. -1, doi. 10.1142/S0219581X13500427
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AN EFFICIENT REVERSE CONVERTER FOR THE NEW FOUR-MODULI SET {2<sup>2n</sup>, 2<sup>n+1</sup> - 1, 2<sup>n/2</sup> + 1, 2<sup>n/2</sup> - 1}.
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- Journal of Circuits, Systems & Computers, 2011, v. 20, n. 7, p. 1341, doi. 10.1142/S0218126611007906
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HARDWARE IMPLEMENTATION AND VERIFICATION OF FIR FILTER UTILIZING M-BIT PDA.
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- Journal of Circuits, Systems & Computers, 2010, v. 19, n. 2, p. 503, doi. 10.1142/S0218126610006207
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- Article
MANIFEST ZUR BILDUNG EINER MATRIX [CODE], SICHERUNG UND VERSCHLEISS DES CULTURAL HERITAGE IN EUROPA.
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- Mitteilungen der Vereinigung Österreichischer Bibliothekarinnen & Bibliothekare, 2010, v. 63, n. 1/2, p. 16
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Analysis of Low Power Consumption Techniques on FPGA for Wireless Devices.
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- Wireless Personal Communications, 2017, v. 95, n. 2, p. 353, doi. 10.1007/s11277-016-3896-2
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- Article
Design of U-Shaped In-Phase Power Divider Employing Ground-Slotted Technique for Wideband Applications.
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- Wireless Personal Communications, 2015, v. 81, n. 1, p. 359, doi. 10.1007/s11277-014-2133-0
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Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA.
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- Wireless Personal Communications, 2014, v. 76, n. 3, p. 569, doi. 10.1007/s11277-014-1725-z
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Circuits arithm?tiques et calculs tensoriels.
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- Journal of the Institute of Mathematics of Jussieu, 2008, v. 7, n. 4, p. 869, doi. 10.1017/S1474748008000248
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- Article
Algebraic Characterization of Reversible Logic Gates.
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- Theory of Computing Systems, 2006, v. 39, n. 2, p. 311, doi. 10.1007/s00224-004-1166-2
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- Article