Works matching DE "COMBINATIONAL circuits"

Results: 235

Synergistic m_GDI-Based ALU Design Using CMOS and VTEAM Memristor Model for Low-Power High-Speed Applications.

Published in:

Journal of Electronic Materials, 2024, v. 53, n. 7, p. 3626, doi. 10.1007/s11664-024-11125-6

By:

Hussain, Syed Ali;
Prasad V, P N S B S V;
Sanki, Pradyut Kumar

Publication type:

Article

A Reversible Multi-Stimuli-Responsive Fluorescence Probe and the Design for Combinational Logic Gate Operations.

Published in:

Macromolecular Rapid Communications, 2014, v. 35, n. 3, p. 303, doi. 10.1002/marc.201300829

By:

Xia, Hongyan;
Xu, Yangyang;
Yang, Guang;
Jiang, Hao;
Zou, Gang;
Zhang, Qijin

Publication type:

Article

A Supramolecular Counter Circuit Based on Cyanine Dye Assembly.

Published in:

Chemistry - A European Journal, 2020, v. 26, n. 58, p. 13235, doi. 10.1002/chem.202001240

By:

Chen, Die;
Wu, Zhiming;
Xu, Xiaoping;
Yang, Shu

Publication type:

Article

Sequential Logic Operations with a Molecular Keypad Lock with Four Inputs and Dual Fluorescence Outputs.

Published in:

Angewandte Chemie, 2014, v. 126, n. 39, p. 10649, doi. 10.1002/ange.201406002

By:

Jiang, Xiong ‐ Jie;
Ng, Dennis K. P.

Publication type:

Article

Chemical reaction network designs for asynchronous logic circuits.

Published in:

Natural Computing, 2018, v. 17, n. 1, p. 109, doi. 10.1007/s11047-017-9665-7

By:

Cardelli, Luca;
Kwiatkowska, Marta;
Whitby, Max

Publication type:

Article

On codes with summation of data bits in concurrent error detection systems.

Published in:

Automation & Remote Control, 2014, v. 75, n. 8, p. 1460, doi. 10.1134/S0005117914080098

By:

Blyudov, A.;
Efanov, D.;
Sapozhnikov, V.;
Sapozhnikov, Vl.

Publication type:

Article

Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs.

Published in:

Automation & Remote Control, 2013, v. 74, n. 7, p. 1164, doi. 10.1134/S0005117913070084

By:

Matrosova, A.;
Ostanin, S.;
Singh, V.

Publication type:

Article

Summation codes for organization of control of combinational circuits.

Published in:

Automation & Remote Control, 2013, v. 74, n. 6, p. 1020, doi. 10.1134/S0005117913060118

By:

Blyudov, A.;
Efanov, D.;
Sapozhnikov, V.;
Sapozhnikov, Vl.

Publication type:

Article

A modified summation code for organizing control of combinatorial circuits.

Published in:

Automation & Remote Control, 2012, v. 73, n. 1, p. 153, doi. 10.1134/S0005117912010122

By:

Blyudov, A.;
Sapozhnikov, V.;
Sapozhnikov, Vl.

Publication type:

Article

Checking of combinational circuits basing on modification sum codes.

Published in:

Automation & Remote Control, 2008, v. 69, n. 8, p. 1411, doi. 10.1134/S0005117908080134

By:

Mekhov, V.;
Sapozhnikov, V.;
Sapozhnikov, Vl.

Publication type:

Article

FROM BOOLE’S LOGIC TO BOOLEAN APPLICATIONS IN COMPUTER SCIENCE.

Published in:

Educational Discourse: Collection of Scientific Papers, 2021, v. 32, n. 4, p. 18, doi. 10.33930/ed.2019.5007.32(4)-2

By:

Awwad, Mohamad

Publication type:

Article

Reconfigurable Si Nanowire Nonvolatile Transistors.

Published in:

Advanced Electronic Materials, 2018, v. 4, n. 1, p. 1, doi. 10.1002/aelm.201700399

By:

Park, So Jeong;
Jeon, Dae‐young;
Piontek, Sabrina;
Grube, Matthias;
Ocker, Johannes;
Sessi, Violetta;
Heinzig, André;
Trommer, Jens;
Kim, Gyu‐tae;
Mikolajick, Thomas;
Weber, Walter M.

Publication type:

Article

Comparative study of serial and parallel heuristics used to design combinational logic circuits.

Published in:

Optimization Methods & Software, 2007, v. 22, n. 3, p. 485, doi. 10.1080/10556780600724979

By:

Alba, Enrique;
Luque, Gabriel;
Coello Coello, CarlosA.;
Hernández Luna, Erika

Publication type:

Article

FUNCTIONAL DECOMPOSITION OF COMBINATIONAL LOGIC CIRCUITS WITH PKMIN.

Published in:

Technical Transactions / Czasopismo Techniczne, 2016, v. 2-E, p. 191, doi. 10.4467/2353737XCT.16.257.6056

By:

MICHALSKI, TOMASZ;
KOKOSIŃSKI, ZBIGNIEW

Publication type:

Article

Randomized generation of error control codes with automata and transducers.

Published in:

RAIRO - Theoretical Informatics & Applications, 2018, v. 52, n. 2-4, p. 169, doi. 10.1051/ita/2018015

By:

Bordihn, Henning;
Nagy, Benedek;
Vaszil, György;
Konstantinidis, Stavros;
Moreira, Nelma;
Reis, Rogério

Publication type:

Article

CNTFET based radiation hardened latch.

Published in:

Australian Journal of Electrical & Electronic Engineering, 2021, v. 18, n. 3, p. 199, doi. 10.1080/1448837X.2021.1958978

By:

Shakeel, Shazia;
Alam, Naushad

Publication type:

Article

Circuits for robust designs.

Published in:

Statistical Papers, 2022, v. 63, n. 5, p. 1537, doi. 10.1007/s00362-021-01285-6

By:

Fontana, Roberto;
Rapallo, Fabio;
Wynn, Henry P.

Publication type:

Article

Potential of photonic crystal fiber for designing optical devices for telecommunication networks.

Published in:

Optical & Quantum Electronics, 2024, v. 56, n. 2, p. 1, doi. 10.1007/s11082-023-05723-7

By:

Goyal, Priyanka;
Kathpal, Namita

Publication type:

Article

Modeling of silicon microring resonator-based programmable logic device for various arithmetic and logic operation in Z-domain.

Published in:

Optical & Quantum Electronics, 2023, v. 55, n. 2, p. 1, doi. 10.1007/s11082-022-04378-0

By:

Kundu, Sumanta;
Hossain, Manjur;
Mandal, Sanjoy

Publication type:

Article

Design and performance analysis of plasmonic reflective codes in combinational circuits for high speed computing.

Published in:

Optical & Quantum Electronics, 2022, v. 54, n. 12, p. 1, doi. 10.1007/s11082-022-04211-8

By:

Uniyal, Shikha;
Choudhary, Kuldeep;
Sachdev, Surbhi;
Kumar, Santosh

Publication type:

Article

Implementation of all-optical 4 bit binary to gray code converter based on cross-phase modulation effect in a phase shifted fiber Bragg grating.

Published in:

Optical & Quantum Electronics, 2022, v. 54, n. 9, p. 1, doi. 10.1007/s11082-022-03980-6

By:

Mahanty, Sushanta;
Kumar, Ajay

Publication type:

Article

Performance analysis of all optical contention detection circuit for high speed optical access networks.

Published in:

Optical & Quantum Electronics, 2022, v. 54, n. 7, p. 1, doi. 10.1007/s11082-022-03647-2

By:

Lovkesh;
Singh, Dilbag;
Singh, Surinder;
Singh, Sukhbir

Publication type:

Article

Design and simulation of efficient combinational circuits based on a new XOR structure in QCA technology.

Published in:

Optical & Quantum Electronics, 2021, v. 53, n. 12, p. 1, doi. 10.1007/s11082-021-03294-z

By:

Safaiezadeh, Behrouz;
Mahdipour, Ebrahim;
Haghparast, Majid;
Sayedsalehi, Samira;
Hosseinzadeh, Mehdi

Publication type:

Article

Implementation of an optical universal one-bit arithmetic logical circuit for high-speed processing combinational circuits.

Published in:

Optical & Quantum Electronics, 2020, v. 52, n. 10, p. N.PAG, doi. 10.1007/s11082-020-02549-5

By:

Choudhary, Kuldeep;
Kaushik, Akash;
Semwal, Ankit;
Mishra, Saurabh;
Kumar, Santosh

Publication type:

Article

Modeling Soft Error Propagation in Near-Threshold Combinational Circuits Using Neural Networks.

Published in:

Journal of Electronic Testing, 2019, v. 35, n. 3, p. 401, doi. 10.1007/s10836-019-05796-x

By:

Hajian, Ali;
Safari, Saeed

Publication type:

Article

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design.

Published in:

Journal of Electronic Testing, 2018, v. 34, n. 1, p. 53, doi. 10.1007/s10836-018-5703-3

By:

Shah, Toral;
Matrosova, Anzhela;
Fujita, Masahiro;
Singh, Virendra

Publication type:

Article

Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits.

Published in:

Journal of Electronic Testing, 2017, v. 33, n. 5, p. 607, doi. 10.1007/s10836-017-5682-9

By:

Hamad, Ghaith;
Ait Mohamed, Otmane;
Savaria, Yvon

Publication type:

Article

A Fast Statistical Soft Error Rate Estimation Method for Nano-scale Combinational Circuits.

Published in:

Journal of Electronic Testing, 2016, v. 32, n. 3, p. 291, doi. 10.1007/s10836-016-5583-3

By:

Raji, Mohsen;
Ghavami, Behnam

Publication type:

Article

A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients.

Published in:

Journal of Electronic Testing, 2014, v. 30, n. 5, p. 595, doi. 10.1007/s10836-014-5476-2

By:

Pahlevanzadeh, Hoda;
Yu, Qiaoyan

Publication type:

Article

A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 331, doi. 10.1007/s10836-013-5359-y

By:

Possamai Bastos, Rodrigo;
Natale, Giorgio;
Flottes, Marie-Lise;
Lu, Feng;
Rouzeyre, Bruno

Publication type:

Article

An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology.

Published in:

Journal of Electronic Testing, 2011, v. 27, n. 2, p. 193, doi. 10.1007/s10836-011-5195-x

By:

Cheng, Chi-Hsuan;
Li, James

Publication type:

Article

Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 5, p. 439, doi. 10.1007/s10836-007-5039-x

By:

Ozgur Sinanoglu

Publication type:

Article

Holistic and Compositional Logics Based on the Bertini Gate.

Published in:

Foundations of Science, 2022, v. 27, n. 1, p. 57, doi. 10.1007/s10699-020-09703-y

By:

Leporini, Roberto

Publication type:

Article

The equal-length redundant code development for the self-checking combinational devices synthesis based on data on their structures.

Published in:

Èlektronnoe Modelirovanie, 2022, v. 44, n. 1, p. 43, doi. 10.15407/emodel.44.01.043

By:

Efanov, D. V.

Publication type:

Article

Typical structure of a duplicate error correction scheme with code control with summation of weighted transitions.

Published in:

Èlektronnoe Modelirovanie, 2020, v. 42, n. 5, p. 38, doi. 10.15407/emodel.42.05.038

By:

Efanov, D. V.;
Sapozhnikov, V. V.;
Sapozhnikov, Vl. V.

Publication type:

Article

Enhance Speed Low Area FPGA Design Using S-Box GF and Pipeline Approach on Logic for AES.

Published in:

Mathematical Modelling of Engineering Problems, 2024, v. 11, n. 3, p. 773, doi. 10.18280/mmep.110322

By:

Lakshmi, K. Janshi;
Sreenivasulu, G.

Publication type:

Article

The Combinator - a computer-based tool for creative idea generation based on a simulation approach.

Published in:

Design Science, 2018, v. 4, p. 1, doi. 10.1017/dsj.2018.7

By:

Ji Han;
Feng Shi;
Liuqing Chen;
Childs, Peter R. N.

Publication type:

Article

Raman scattering in lead selenide films at a low excitation level.

Published in:

Optics & Spectroscopy, 2015, v. 119, n. 6, p. 938, doi. 10.1134/S0030400X15120140

By:

Kuzivanov, M.;
Zimin, S.;
Fedorov, A.;
Baranov, A.

Publication type:

Article

Design an All-Optical Combinational Logic Circuits Based on Nano-Ring Insulator-Metal-Insulator Plasmonic Waveguides.

Published in:

Photonics, 2019, v. 6, n. 1, p. 30, doi. 10.3390/photonics6010030

By:

Abdulnabi, Saif Hasan;
Abbas, Mohammed Nadhim

Publication type:

Article

Adaptation of counters redundant bits with the provision of dual supply and modified clock gating to favour of low power in VLSI.

Published in:

Indian Journal of Pure & Applied Physics, 2020, v. 58, n. 10, p. 750

By:

Sulaiman, S. Mohamed;
Jaison, B.;
Bennet, M. Anto;
Vaithiyanathan, D.

Publication type:

Article

Integrated non-volatile plasmonic switches based on phase-change-materials and their application to plasmonic logic circuits.

Published in:

Scientific Reports, 2021, v. 11, n. 1, p. 1, doi. 10.1038/s41598-021-98418-6

By:

Ghosh, Rajib Ratan;
Dhawan, Anuj

Publication type:

Article

Design of 4 bits Combinational Lock Using VHDL.

Published in:

International Journal of Electrical, Electronics & Computer Systems, 2014, v. 19, n. 2, p. 15

By:

Ogeh, Jenny Ebitonere

Publication type:

Article

Power Optimization for Mixed Polarity Reed–Muller Circuits Based on Multilevel Adaptive Memetic Algorithm.

Published in:

International Journal of Intelligent Systems, 2023, p. 1, doi. 10.1155/2023/3510001

By:

Zhou, Yuhao;
He, Zhenxue;
Zhang, Yan;
Liu, Jia;
Wang, Tao;
Xiao, Limin;
Wang, Xiang

Publication type:

Article

Accelerating stochastic‐based reliability estimation for combinational circuits at RTL using GPU parallel computing.

Published in:

International Journal of Intelligent Systems, 2022, v. 37, n. 11, p. 8309, doi. 10.1002/int.22940

By:

Xiao, Jie;
Ji, Qiou;
Shen, Qing;
Jiang, Jianhui;
Huang, Yujiao;
Lou, Jungang

Publication type:

Article

Delay optimization for ternary fixed polarity Reed–Muller circuits based on multilevel adaptive quantum genetic algorithm.

Published in:

International Journal of Intelligent Systems, 2021, v. 36, n. 10, p. 5981, doi. 10.1002/int.22538

By:

Zhenxue, He;
Xiaoqian, Wu;
Chao, Wang;
Zhisheng, Huo;
Limin, Xiao;
Xiang, Wang

Publication type:

Article

On-chip bacterial foraging training in silicon photonic circuits for projection-enabled nonlinear classification.

Published in:

Nature Communications, 2022, v. 13, n. 1, p. 1, doi. 10.1038/s41467-022-30906-3

By:

Cong, Guangwei;
Yamamoto, Noritsugu;
Inoue, Takashi;
Maegami, Yuriko;
Ohno, Morifumi;
Kita, Shota;
Namiki, Shu;
Yamada, Koji

Publication type:

Article

Group leaders optimization algorithm.

Published in:

Molecular Physics, 2011, v. 109, n. 5, p. 761, doi. 10.1080/00268976.2011.552444

By:

Daskin, Anmer;
Kais, Sabre

Publication type:

Article

Design of 16-Bit ALU with Booths Multiplier Using Radix-4 and Its FPGA Implementation.

Published in:

IUP Journal of Electrical & Electronics Engineering, 2020, v. 13, n. 4, p. 30

By:

Srivastava, Prerna;
Singh, Rakesh Kumar

Publication type:

Article

Optimization and Synthesis of Combinational Circuits Using Improved mGDI Technique.

Published in:

IUP Journal of Electrical & Electronics Engineering, 2017, v. 10, n. 1, p. 18

By:

Devi, Monika;
Duhan, Manoj

Publication type:

Article

Enhancing the Reliability of Combinational Circuits by Adding Redundancy Using Fault Tree Analysis.

Published in:

IUP Journal of Electrical & Electronics Engineering, 2015, v. 8, n. 4, p. 14

By:

Deepak;
Duhan, Manoj

Publication type:

Article