Works matching DE "COMBINATIONAL circuits"
Results: 227
OPTIMIZATION PROBLEM FOR NUMBER OF LOGIC GATES NEEDED TO IMPLEMENT MULTIPLE BOOLEAN FUNCTIONS USING DECODER.
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- Automation of Technological & Business Processes / Avtomatizaciâ Tehnologiceskih i Biznes-Processov, 2024, v. 16, n. 4, p. 110, doi. 10.15673/atbp.v16i4.3018
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- Article
The Language of Search.
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- Journal of Artificial Intelligence Research, 2007, v. 29, p. 191, doi. 10.1613/jair.2097
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- Article
OPTIMIZATION PROBLEM FOR NUMBER OF LOGIC GATES NEEDED TO IMPLEMENT MULTIPLE BOOLEAN FUNCTIONS USING DECODER.
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- Automation of Technological & Business Processes / Avtomatizaciâ Tehnologiceskih i Biznes-Processov, 2024, v. 16, n. 3, p. 11, doi. 10.15673/atbp.v16i3.2915
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- Article
Tracking Students' Learning Progress on Troubleshooting Logical Circuits Using Web Application.
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- TEM Journal, 2023, v. 12, n. 3, p. 1323, doi. 10.18421/TEM123-12
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Design of Novel Efficient Multiplexer Architecture for Quantum-dot Cellular Automata.
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- Journal of Nano- & Electronic Physics, 2017, v. 9, n. 1, p. 01012-1, doi. 10.21272/jnep.9(1).01012
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- Article
A method of synthesis of irredundant circuits admitting single fault detection tests of constant length.
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- Discrete Mathematics & Applications, 2019, v. 29, n. 1, p. 35, doi. 10.1515/dma-2019-0005
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Method of synthesis of easily testable circuits admitting single fault detection tests of constant length.
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- Discrete Mathematics & Applications, 2014, v. 24, n. 4, p. 227, doi. 10.1515/dma-2014-0021
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CryptoDL: Predicting Dyslexia Biomarkers from Encrypted Neuroimaging Dataset Using Energy-Efficient Residue Number System and Deep Convolutional Neural Network.
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- Symmetry (20738994), 2020, v. 12, n. 5, p. 836, doi. 10.3390/sym12050836
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A Note on the Minimum Size of a Point Set Containing Three Nonintersecting Empty Convex Polygons.
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- Symmetry (20738994), 2018, v. 10, n. 10, p. 447, doi. 10.3390/sym10100447
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Formal Derivation of a Particular Input of a Single AND (OR) Gate in Terms of Its Output and Other Inputs.
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- Journal of King Abdulaziz University: Engineering Sciences, 2015, v. 26, n. 2, p. 51, doi. 10.4197/Eng.26-2.3
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Analysis of a Low-profile L-Shaped Microstrip Patch Antenna with DGS for ISM and Sub-6GHz Applications.
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- International Journal of Microwave & Optical Technology, 2024, v. 19, n. 3, p. 273
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A Method for Reducing Memory Effect in RF Amplifier with FIR Filter.
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- Majlesi Journal of Electrical Engineering, 2009, v. 3, n. 1, p. 1
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Phenomenological analysis of rapidity distribution of negative pions in central <sup>12</sup>C+<sup>12</sup>C collisions at √s<sub>nn</sub>= 3.14 GeV.
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- International Journal of Modern Physics E: Nuclear Physics, 2015, v. 24, n. 6, p. 1550049-1, doi. 10.1142/S0218301315500494
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Energy Efficient 4-2 and 5-2 Compressor for Arithmetic Circuits.
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- Journal of Active & Passive Electronic Devices, 2023, v. 17, n. 3, p. 185
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Novel Quantum Adder Circuit Design Using CNOT Gate.
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- Journal of Active & Passive Electronic Devices, 2023, v. 17, n. 2, p. 159
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Editorial.
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- Journal of Active & Passive Electronic Devices, 2023, v. 17, n. 2, p. 97
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A CMOS-Based Dual Logic Mode Gate for Analysis of Logical Effort in Sequential and Combinational Circuit.
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- International Review on Computers & Software, 2015, v. 10, n. 1, p. 27, doi. 10.15866/irecos.v10i1.5260
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- Article
CoCEC: An Automatic Combinational Circuit Equivalence Checker Based on the Interactive Theorem Prover.
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- Complexity, 2021, p. 1, doi. 10.1155/2021/5525539
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- Article
Relations between the Circumference and e-Circumference of a Matroid.
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- Graphs & Combinatorics, 2008, v. 24, n. 2, p. 101, doi. 10.1007/s00373-008-0772-1
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- Article
FROM BOOLE’S LOGIC TO BOOLEAN APPLICATIONS IN COMPUTER SCIENCE.
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- Educational Discourse: Collection of Scientific Papers, 2021, v. 32, n. 4, p. 18, doi. 10.33930/ed.2019.5007.32(4)-2
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Effectiveness and safety of combinational therapy compared with intensified statin monotherapy in patients with coronary heart disease.
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- Experimental & Therapeutic Medicine, 2018, v. 15, n. 6, p. 4683, doi. 10.3892/etm.2018.6024
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- Article
COMPARATIVE ANALYSIS AND FPGA IMPLEMENTATION OF VEDIC AND BOOTH MULTIPLIER.
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- i-Manager's Journal on Electronics Engineering, 2015, v. 6, n. 2, p. 29
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- Article
Test Pattern Generation Algorithm Using Structurally Synthesized BDD.
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- GSTF Journal on Computing, 2011, v. 1, n. 2, p. 6, doi. 10.5176/2010-2283_1.2.31
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- Article
Power Optimization for Mixed Polarity Reed–Muller Circuits Based on Multilevel Adaptive Memetic Algorithm.
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- International Journal of Intelligent Systems, 2023, p. 1, doi. 10.1155/2023/3510001
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Accelerating stochastic‐based reliability estimation for combinational circuits at RTL using GPU parallel computing.
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- International Journal of Intelligent Systems, 2022, v. 37, n. 11, p. 8309, doi. 10.1002/int.22940
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Delay optimization for ternary fixed polarity Reed–Muller circuits based on multilevel adaptive quantum genetic algorithm.
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- International Journal of Intelligent Systems, 2021, v. 36, n. 10, p. 5981, doi. 10.1002/int.22538
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Group leaders optimization algorithm.
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- Molecular Physics, 2011, v. 109, n. 5, p. 761, doi. 10.1080/00268976.2011.552444
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Functional Delay Test Generation Approach Using a Software Prototype of the Circuit.
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- Computer Science & Information Systems, 2013, v. 10, n. 3, p. 1165, doi. 10.2298/CSIS120416019B
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The Relationship between IT Outsourcing and Business and IT Alignment: an Explorative Study.
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- Computer Science & Information Systems, 2013, v. 10, n. 3, p. 973, doi. 10.2298/CSIS120526020S
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Microcontroller implementation of lookup table-based control functions with special emphasis on sequential control according to IEC 61131-3.
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- International Journal of Electrical Engineering Education, 2015, v. 52, n. 2, p. 111, doi. 10.1177/0020720915571492
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- Article
Online Laboratory in Digital Electronics Using NI ELVIS II+.
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- International Journal of Interactive Mobile Technologies, 2015, v. 9, n. 2, p. 26, doi. 10.3991/ijim.v9i2.4385
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Optimization of Combinational Logic Circuits with Genetic Programming.
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- Electronics & Electrical Engineering, 2013, v. 19, n. 7, p. 86, doi. 10.5755/j01.eee.19.7.5169
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Factor of Randomness in Functional Delay Fault Test Generation for Full Scan Circuits.
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- Electronics & Electrical Engineering, 2010, n. 105, p. 39
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- Article
Development of Combinational Circuits by Encoding on the Basis of Developmental Biology.
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- Computational Intelligence & Neuroscience, 2020, p. 1, doi. 10.1155/2020/7696398
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An Efficient Software Tool based on SCOAP for Testability Analysis of Combinational Circuits.
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- International Journal of Simulation: Systems, Science & Technology, 2019, v. 20, n. 1, p. 1, doi. 10.5013/IJSSST.a.20.01.30
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Evaluation of Dual Rail Complete Detection Circuitry using Asynchronous Delay Insensitive Frameworks.
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- International Journal of Simulation: Systems, Science & Technology, 2018, v. 19, n. 3, p. 1, doi. 10.5013/IJSSST.a.19.03.10
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Potential of photonic crystal fiber for designing optical devices for telecommunication networks.
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- Optical & Quantum Electronics, 2024, v. 56, n. 2, p. 1, doi. 10.1007/s11082-023-05723-7
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Modeling of silicon microring resonator-based programmable logic device for various arithmetic and logic operation in Z-domain.
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- Optical & Quantum Electronics, 2023, v. 55, n. 2, p. 1, doi. 10.1007/s11082-022-04378-0
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Design and performance analysis of plasmonic reflective codes in combinational circuits for high speed computing.
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- Optical & Quantum Electronics, 2022, v. 54, n. 12, p. 1, doi. 10.1007/s11082-022-04211-8
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Implementation of all-optical 4 bit binary to gray code converter based on cross-phase modulation effect in a phase shifted fiber Bragg grating.
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- Optical & Quantum Electronics, 2022, v. 54, n. 9, p. 1, doi. 10.1007/s11082-022-03980-6
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Performance analysis of all optical contention detection circuit for high speed optical access networks.
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- Optical & Quantum Electronics, 2022, v. 54, n. 7, p. 1, doi. 10.1007/s11082-022-03647-2
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Design and simulation of efficient combinational circuits based on a new XOR structure in QCA technology.
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- Optical & Quantum Electronics, 2021, v. 53, n. 12, p. 1, doi. 10.1007/s11082-021-03294-z
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- Article
Implementation of an optical universal one-bit arithmetic logical circuit for high-speed processing combinational circuits.
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- Optical & Quantum Electronics, 2020, v. 52, n. 10, p. N.PAG, doi. 10.1007/s11082-020-02549-5
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Chemical reaction network designs for asynchronous logic circuits.
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- Natural Computing, 2018, v. 17, n. 1, p. 109, doi. 10.1007/s11047-017-9665-7
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Logic Minimization Techniques with Applications to Cryptology.
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- Journal of Cryptology, 2013, v. 26, n. 2, p. 280, doi. 10.1007/s00145-012-9124-7
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- Article
A Novel Scan Architecture for Low Power Scan-Based Testing.
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- VLSI Design, 2015, v. 2015, p. 1, doi. 10.1155/2015/264071
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Verification of Mixed-Signal Systems with Affine Arithmetic Assertions.
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- VLSI Design, 2013, p. 1, doi. 10.1155/2013/239064
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Adaptation of counters redundant bits with the provision of dual supply and modified clock gating to favour of low power in VLSI.
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- Indian Journal of Pure & Applied Physics, 2020, v. 58, n. 10, p. 750
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- Article
ARITHMETIC-LOGIC SINGLE-ELECTRON NANOCIRCUITS.
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- Electronics & Control Systems, 2023, v. 76, n. 2, p. 68, doi. 10.18372/1990-5548.76.17670
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Research on the optimal model for the evaluation of new power system investment projects based on the cloud model–DS evidence theory–TOPSIS method.
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- Energy Science & Engineering, 2024, v. 12, n. 1, p. 22, doi. 10.1002/ese3.1570
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- Article