Works matching DE "COMBINATIONAL circuits"
Results: 225
Potential of photonic crystal fiber for designing optical devices for telecommunication networks.
- Published in:
- Optical & Quantum Electronics, 2024, v. 56, n. 2, p. 1, doi. 10.1007/s11082-023-05723-7
- By:
- Publication type:
- Article
Modeling of silicon microring resonator-based programmable logic device for various arithmetic and logic operation in Z-domain.
- Published in:
- Optical & Quantum Electronics, 2023, v. 55, n. 2, p. 1, doi. 10.1007/s11082-022-04378-0
- By:
- Publication type:
- Article
Design and performance analysis of plasmonic reflective codes in combinational circuits for high speed computing.
- Published in:
- Optical & Quantum Electronics, 2022, v. 54, n. 12, p. 1, doi. 10.1007/s11082-022-04211-8
- By:
- Publication type:
- Article
Implementation of all-optical 4 bit binary to gray code converter based on cross-phase modulation effect in a phase shifted fiber Bragg grating.
- Published in:
- Optical & Quantum Electronics, 2022, v. 54, n. 9, p. 1, doi. 10.1007/s11082-022-03980-6
- By:
- Publication type:
- Article
Performance analysis of all optical contention detection circuit for high speed optical access networks.
- Published in:
- Optical & Quantum Electronics, 2022, v. 54, n. 7, p. 1, doi. 10.1007/s11082-022-03647-2
- By:
- Publication type:
- Article
Design and simulation of efficient combinational circuits based on a new XOR structure in QCA technology.
- Published in:
- Optical & Quantum Electronics, 2021, v. 53, n. 12, p. 1, doi. 10.1007/s11082-021-03294-z
- By:
- Publication type:
- Article
Implementation of an optical universal one-bit arithmetic logical circuit for high-speed processing combinational circuits.
- Published in:
- Optical & Quantum Electronics, 2020, v. 52, n. 10, p. N.PAG, doi. 10.1007/s11082-020-02549-5
- By:
- Publication type:
- Article
Chemical reaction network designs for asynchronous logic circuits.
- Published in:
- Natural Computing, 2018, v. 17, n. 1, p. 109, doi. 10.1007/s11047-017-9665-7
- By:
- Publication type:
- Article
A sliced architecture using novel configurable logic modules in quantum dot cellular automata for application of field-programmable gate arrays.
- Published in:
- Journal of Supercomputing, 2023, v. 79, n. 4, p. 4105, doi. 10.1007/s11227-022-04812-w
- By:
- Publication type:
- Article
Logic Realization of Galois Field for AES SBOX using Quantum Dot Cellular Automata.
- Published in:
- Journal of Supercomputing, 2023, v. 79, n. 3, p. 3024, doi. 10.1007/s11227-022-04779-8
- By:
- Publication type:
- Article
Approximate Evaluation of the Efficiency of Synchronous and Self-Timed Methodologies in Problems of Designing Failure-Tolerant Computing and Control Systems.
- Published in:
- Automation & Remote Control, 2022, v. 83, n. 2, p. 264, doi. 10.1134/S0005117922020084
- By:
- Publication type:
- Article
Boolean-Complement Based Fault-Tolerant Electronic Device Architectures.
- Published in:
- Automation & Remote Control, 2021, v. 82, n. 8, p. 1403, doi. 10.1134/S0005117921080075
- By:
- Publication type:
- Article
Sum Codes with Efficient Detection of Twofold Errors for Organization of Concurrent Error-Detection Systems of Logical Devices.
- Published in:
- Automation & Remote Control, 2018, v. 79, n. 4, p. 665, doi. 10.1134/S0005117918040082
- By:
- Publication type:
- Article
Fast median-finding word comparator array.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2017, v. 53, n. 21, p. 1402, doi. 10.1049/el.2017.1811
- By:
- Publication type:
- Article
FROM BOOLE’S LOGIC TO BOOLEAN APPLICATIONS IN COMPUTER SCIENCE.
- Published in:
- Educational Discourse: Collection of Scientific Papers, 2021, v. 32, n. 4, p. 18, doi. 10.33930/ed.2019.5007.32(4)-2
- By:
- Publication type:
- Article
High Throughput on-the-fly Implementation for AES.
- Published in:
- Grenze International Journal of Engineering & Technology (GIJET), 2021, v. 7, n. 2, p. 106
- By:
- Publication type:
- Article
OPTIMIZATION PROBLEM FOR NUMBER OF LOGIC GATES NEEDED TO IMPLEMENT MULTIPLE BOOLEAN FUNCTIONS USING DECODER.
- Published in:
- Automation of Technological & Business Processes / Avtomatizaciâ Tehnologiceskih i Biznes-Processov, 2024, v. 16, n. 3, p. 11, doi. 10.15673/atbp.v16i3.2915
- By:
- Publication type:
- Article
Spin-Based Fully Nonvolatile Full-Adder Circuit for Computing in Memory.
- Published in:
- SPIN (2010-3247), 2019, v. 9, n. 1, p. N.PAG, doi. 10.1142/S2010324719500073
- By:
- Publication type:
- Article
Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions.
- Published in:
- Aerospace (MDPI Publishing), 2020, v. 7, n. 2, p. 12, doi. 10.3390/aerospace7020012
- By:
- Publication type:
- Article
Unknown Attack Detection: Combining Relabeling and Hybrid Intrusion Detection.
- Published in:
- Computers, Materials & Continua, 2021, v. 68, n. 3, p. 3289, doi. 10.32604/cmc.2021.017502
- By:
- Publication type:
- Article
Design of 16-Bit ALU with Booths Multiplier Using Radix-4 and Its FPGA Implementation.
- Published in:
- IUP Journal of Electrical & Electronics Engineering, 2020, v. 13, n. 4, p. 30
- By:
- Publication type:
- Article
Optimization and Synthesis of Combinational Circuits Using Improved mGDI Technique.
- Published in:
- IUP Journal of Electrical & Electronics Engineering, 2017, v. 10, n. 1, p. 18
- By:
- Publication type:
- Article
Enhancing the Reliability of Combinational Circuits by Adding Redundancy Using Fault Tree Analysis.
- Published in:
- IUP Journal of Electrical & Electronics Engineering, 2015, v. 8, n. 4, p. 14
- By:
- Publication type:
- Article
Online Laboratory in Digital Electronics Using NI ELVIS II+.
- Published in:
- International Journal of Interactive Mobile Technologies, 2015, v. 9, n. 2, p. 26, doi. 10.3991/ijim.v9i2.4385
- By:
- Publication type:
- Article
Development of Combinational Circuits by Encoding on the Basis of Developmental Biology.
- Published in:
- Computational Intelligence & Neuroscience, 2020, p. 1, doi. 10.1155/2020/7696398
- By:
- Publication type:
- Article
Relations between the Circumference and e-Circumference of a Matroid.
- Published in:
- Graphs & Combinatorics, 2008, v. 24, n. 2, p. 101, doi. 10.1007/s00373-008-0772-1
- By:
- Publication type:
- Article
ASIC Implementation of An Effective Reversible R2B Fft for 5G Technology Using Reversible Logic.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2022, v. 4, n. 2, p. 5, doi. 10.31838/jvcs/04.02.02
- By:
- Publication type:
- Article
Enhance Speed Low Area FPGA Design Using S-Box GF and Pipeline Approach on Logic for AES.
- Published in:
- Mathematical Modelling of Engineering Problems, 2024, v. 11, n. 3, p. 773, doi. 10.18280/mmep.110322
- By:
- Publication type:
- Article
CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers.
- Published in:
- Informacije MIDEM: Journal of Microelectronics, Electronic Components & Materials, 2020, v. 50, n. 2, p. 115, doi. 10.33180/InfMIDEM2020.204
- By:
- Publication type:
- Article
Quick detection of faults in combinational networks designed in minterm format by computing a single novel parameter.
- Published in:
- International Journal of Computer Mathematics, 2009, v. 86, n. 3, p. 393, doi. 10.1080/00207160701652953
- By:
- Publication type:
- Article
Design and Validation of Low-Power Secure and Dependable Elliptic Curve Cryptosystem.
- Published in:
- Journal of Low Power Electronics & Applications, 2021, v. 11, n. 4, p. 43, doi. 10.3390/jlpea11040043
- By:
- Publication type:
- Article
Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology.
- Published in:
- Journal of Low Power Electronics & Applications, 2015, v. 5, n. 2, p. 81, doi. 10.3390/jlpea5020081
- By:
- Publication type:
- Article
Randomized generation of error control codes with automata and transducers.
- Published in:
- RAIRO - Theoretical Informatics & Applications, 2018, v. 52, n. 2-4, p. 169, doi. 10.1051/ita/2018015
- By:
- Publication type:
- Article
A Method for Reducing Memory Effect in RF Amplifier with FIR Filter.
- Published in:
- Majlesi Journal of Electrical Engineering, 2009, v. 3, n. 1, p. 1
- By:
- Publication type:
- Article
CNTFET based radiation hardened latch.
- Published in:
- Australian Journal of Electrical & Electronic Engineering, 2021, v. 18, n. 3, p. 199, doi. 10.1080/1448837X.2021.1958978
- By:
- Publication type:
- Article
POWER OPTIMIZATION OF COMBINATIONAL CIRCUITS MAPPED ON LUT-BASED FPGAS.
- Published in:
- Annals of DAAAM & Proceedings, 2009, p. 1231
- By:
- Publication type:
- Article
A Novel Double-Gate MOSFET Architecture as an Inverter.
- Published in:
- IETE Journal of Research, 2023, v. 69, n. 11, p. 8218, doi. 10.1080/03772063.2022.2048712
- By:
- Publication type:
- Article
HsClone Genetic Algorithm Implementation on a Combinational Circuit.
- Published in:
- IETE Journal of Research, 2023, v. 69, n. 3, p. 1373, doi. 10.1080/03772063.2020.1867010
- By:
- Publication type:
- Article
An Efficient Quantum-Dot Cellular Automata Full Adder Based on a New Convertible 7-Input Majority-Not Gate.
- Published in:
- IETE Journal of Research, 2023, v. 69, n. 1, p. 558, doi. 10.1080/03772063.2020.1838338
- By:
- Publication type:
- Article
Compact Corner Truncated Fractal Slot Antenna for Cognitive Radio Sensor Network.
- Published in:
- IETE Journal of Research, 2023, v. 69, n. 1, p. 460, doi. 10.1080/03772063.2020.1829999
- By:
- Publication type:
- Article
Test Pattern Generator for MV-Based QCA Combinational Circuit Targeting MMC Fault Models.
- Published in:
- IETE Journal of Research, 2022, v. 68, n. 3, p. 1812, doi. 10.1080/03772063.2019.1674195
- By:
- Publication type:
- Article
Design and Analysis of Memristor-based Combinational Circuits.
- Published in:
- IETE Journal of Research, 2020, v. 66, n. 2, p. 182, doi. 10.1080/03772063.2018.1486741
- By:
- Publication type:
- Article
Power-delay Trade-offs in CMOS Circuits Using Self-bias Transistors.
- Published in:
- IETE Journal of Research, 2012, v. 58, n. 1, p. 24, doi. 10.4103/0377-2063.94078
- By:
- Publication type:
- Article
Microcontroller implementation of lookup table-based control functions with special emphasis on sequential control according to IEC 61131-3.
- Published in:
- International Journal of Electrical Engineering Education, 2015, v. 52, n. 2, p. 111, doi. 10.1177/0020720915571492
- By:
- Publication type:
- Article
A CMOS-Based Dual Logic Mode Gate for Analysis of Logical Effort in Sequential and Combinational Circuit.
- Published in:
- International Review on Computers & Software, 2015, v. 10, n. 1, p. 27, doi. 10.15866/irecos.v10i1.5260
- By:
- Publication type:
- Article
Design of all-optical parallel multipliers using semiconductor optical amplifier-based Mach–Zehnder interferometers.
- Published in:
- Journal of Supercomputing, 2021, v. 77, n. 7, p. 7315, doi. 10.1007/s11227-020-03543-0
- By:
- Publication type:
- Article
Implementation of multi-precision floating point divider for high speed signal processing applications.
- Published in:
- Journal of Supercomputing, 2019, v. 75, n. 9, p. 6038, doi. 10.1007/s11227-019-02902-w
- By:
- Publication type:
- Article
A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients.
- Published in:
- Journal of Electronic Testing, 2014, v. 30, n. 5, p. 595, doi. 10.1007/s10836-014-5476-2
- By:
- Publication type:
- Article
A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 3, p. 331, doi. 10.1007/s10836-013-5359-y
- By:
- Publication type:
- Article
An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology.
- Published in:
- Journal of Electronic Testing, 2011, v. 27, n. 2, p. 193, doi. 10.1007/s10836-011-5195-x
- By:
- Publication type:
- Article