Works matching DE "CMOS logic circuits"

Results: 54

Demonstration of PdSe2 CMOS Using Same Metal Contact in PdSe2 n‐/p‐MOSFETs through Thickness‐Dependent Phase Transition.

Published in:

Advanced Electronic Materials, 2022, v. 8, n. 11, p. 1, doi. 10.1002/aelm.202200485

By:

Seo, Jae Eun;
Park, Eunpyo;
Das, Tanmoy;
Kwak, Joon Young;
Chang, Jiwon

Publication type:

Article

On the role of astrocyte analog circuit in neural frequency adaptation.

Published in:

Neural Computing & Applications, 2017, v. 28, n. 5, p. 1109, doi. 10.1007/s00521-015-2112-8

By:

Ranjbar, Mahnaz;
Amiri, Mahmood

Publication type:

Article

NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors.

Published in:

Scientific Reports, 2022, v. 12, n. 1, p. 1, doi. 10.1038/s41598-022-07368-0

By:

Yang, Yejin;
Jeon, Juhee;
Son, Jaemin;
Cho, Kyoungah;
Kim, Sangsig

Publication type:

Article

Design Analysis of AND (2T) and OR (2T) Based Low Power Full Adder Circuit.

Published in:

International Journal of Advanced Research in Computer Science, 2014, v. 5, n. 4, p. 111

By:

Kumar, K. N. Mahesh;
Bhargav, D. Harish;
Jyothi, E. Arun

Publication type:

Article

Charge balancing symmetric pre‐resolve adiabatic logic against power analysis attacks.

Published in:

IET Information Security (Wiley-Blackwell), 2019, v. 13, n. 6, p. 692, doi. 10.1049/iet-ifs.2018.5136

By:

Ashok, Prathiba;
Vettuvanam Somasundaram, Kanchana Bhaaskaran

Publication type:

Article

Simple power analysis applied to nonlinear feedback shift registers.

Published in:

IET Information Security (Wiley-Blackwell), 2014, v. 8, n. 3, p. 188, doi. 10.1049/iet-ifs.2012.0186

By:

Zadeh, Abdulah Abdulah;
Heys, Howard M.

Publication type:

Article

Power saving bidirectional optical transceiver design and fabrication.

Published in:

Optical & Quantum Electronics, 2015, v. 47, n. 8, p. 3101, doi. 10.1007/s11082-015-0198-y

By:

Sangirov, Jamshid;
Rakib-Uddin, Mohammad;
Ukaegbu, Ikechi;
Lee, Tae;
Park, Hyo

Publication type:

Article

266-2133 MHz phase shifter using all-digital delay-locked loop and triangular-modulated phase interpolator for LPDDR4X interface.

Published in:

Electronics Letters (Wiley-Blackwell), 2017, v. 53, n. 12, p. 766, doi. 10.1049/el.2017.1291

By:

Chae, J.-H.;
Kim, M.;
Ko, H.;
Jeong, Y.;
Park, J.;
Hong, G.-M.;
Jeong, D.-K.;
Kim, S.

Publication type:

Article

Optimal pipeline stage balancing in the presence of large isolated interconnect delay.

Published in:

Electronics Letters (Wiley-Blackwell), 2017, v. 53, n. 4, p. 229, doi. 10.1049/el.2016.4262

By:

Olivieri, M.;
Menichelli, F.;
Mastrandrea, A.

Publication type:

Article

Nano-power tunable bump circuit using wide-input-range pseudo-differential transconductor.

Published in:

Electronics Letters (Wiley-Blackwell), 2014, v. 50, n. 13, p. 921, doi. 10.1049/el.2014.0920

By:

Junjie Lu;
Tan Yang;
Jahan, M. S.;
Holleman, J.

Publication type:

Article

Compact inductorless CMOS low-noise amplifier for reconfigurable radio.

Published in:

Electronics Letters (Wiley-Blackwell), 2014, v. 50, n. 12, p. 892, doi. 10.1049/el.2014.1031

By:

Slimane, Abdelhalim;
Haddad, Fayrouz;
Bourdel, Sylvain;
Tedjini-Baïliche, Sid Ahmed;
Belaroussi, Mohand Tahar;
Mohamed, Trabelsi;
Barthélemy, Hervé

Publication type:

Article

Distributed range-free localisation algorithm for wireless sensor networks.

Published in:

Electronics Letters (Wiley-Blackwell), 2014, v. 50, n. 12, p. 894, doi. 10.1049/el.2014.0787

By:

Liangyin Chen;
Miao Li;
Kai Liu;
Zhenlei Liu;
Jingyu Zhang;
Tong Peng;
Yan Liu;
Yongjun Xu;
Qian Luo;
Tian He

Publication type:

Article

Challenges for Nanoscale CMOS Logic Based on Two-Dimensional Materials.

Published in:

Nanomaterials (2079-4991), 2022, v. 12, n. 20, p. 3548, doi. 10.3390/nano12203548

By:

Knobloch, Theresia;
Selberherr, Siegfried;
Grasser, Tibor

Publication type:

Article

Delay Insensitive Ternary CMOS Logic for Secure Hardware.

Published in:

Journal of Low Power Electronics & Applications, 2015, v. 5, n. 3, p. 183, doi. 10.3390/jlpea5030183

By:

Nair, Ravi S. P.;
Smith, Scott C.;
Jia Di

Publication type:

Article

Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology.

Published in:

Journal of Low Power Electronics & Applications, 2015, v. 5, n. 2, p. 81, doi. 10.3390/jlpea5020081

By:

Liang Zhou;
Parameswaran, Ravi;
Parsan, Farhad A.;
Smith, Scott C.;
Jia Di

Publication type:

Article

A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention.

Published in:

Journal of Low Power Electronics & Applications, 2015, v. 5, n. 2, p. 57, doi. 10.3390/jlpea5020057

By:

Hiienkari, Markus;
Teittinen, Jukka;
Koskinen, Lauri;
Turnquist, Matthew;
Mäkipää, Jani;
Rantala, Arto;
Sopanen, Matti;
Kaltiokallio, Mikko

Publication type:

Article

Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Environment.

Published in:

International Journal of Nanoelectronics & Materials, 2019, v. 12, n. 2, p. 205

By:

Bhoi, Bandan;
Misra, Neeraj Kumar;
Jamal, Lafifa;
Pradhan, Manoranjan

Publication type:

Article

Circuit Level Implementation for Insulated Shallow Extension Silicon on Nothing (ISE-SON) MOSFET: A Novel Device Architecture.

Published in:

IETE Journal of Research, 2013, v. 59, n. 4, p. 404, doi. 10.4103/0377-2063.118053

By:

Kumari, Vandana;
Saxena, Manoj;
Gupta, Radhey Shayam;
Gupta, Mridula

Publication type:

Article

Accurate Calculation of Unreliability of CMOS Logic Cells and Circuits.

Published in:

Journal of Circuits, Systems & Computers, 2020, v. 29, n. 13, p. N.PAG, doi. 10.1142/S0218126620502023

By:

Beg, Azam

Publication type:

Article

Comparative Study Between Two Novel BJT-DVCC and CMOS-DVCC.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500748

By:

Fathabadi, Hassan

Publication type:

Article

60 GHz-Band Low-Noise Amplifier.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S021812661750075X

By:

Amin, Najam Muhammad;
Shen, Lianfeng;
Wang, Zhi-Gong;
Akhter, Muhammad Ovais;
Afridi, Muhammad Tariq

Publication type:

Article

A CMOS LNA Partially Degenerated Topology Proposal Using Active Inductors.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500785

By:

Cambero, E. V. V.;
Capovilla, C. E.;
Casella, I. R. S.;
Munoz, R. R.;
Araujo, H. X.

Publication type:

Article

Design and Optimization of Differential Ring Oscillator for IR-UWB Applications in 0.18 m CMOS Technology.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500803

By:

Gargouri, Nadia;
Issa, Dalenda Ben;
Sakka, Zied;
Kachouri, Abdennaceur;
Samet, Mounir

Publication type:

Article

An Energy Efficient Logic Approach to Implement CMOS Full Adder.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500840

By:

Kumar, Pankaj;
Sharma, Rajender Kumar

Publication type:

Article

ANFIS Based Thermal Estimation of Ultradeep Submicron Digital Circuit Design.

Published in:

Journal of Integrated Circuits & Systems, 2021, v. 16, n. 3, p. 1, doi. 10.29292/jics.v16i3.507

By:

Kalra, Shruti;
Beniwal, Ruby

Publication type:

Article

CMOS X‐band pole‐converging triple‐cascode LNA with low‐noise and wideband performance.

Published in:

IET Circuits, Devices & Systems (Wiley-Blackwell), 2022, v. 16, n. 1, p. 26, doi. 10.1049/cds2.12081

By:

Cao, Cheng;
Li, Yubing;
Wang, Zhe;
Huang, Zemeng;
Tan, Tao;
Chen, Deyang;
Li, Xiuping

Publication type:

Article

Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology.

Published in:

Electronics (2079-9292), 2024, v. 13, n. 15, p. 2993, doi. 10.3390/electronics13152993

By:

Emir, Recep;
Yamacli, Dilek Surekci;
Yamacli, Serhan;
Tekin, Sezai Alper

Publication type:

Article

Design and Validation of a V-Gate n-MOSFET-Based RH CMOS Logic Circuit with Tolerance to the TID Effect.

Published in:

Electronics (2079-9292), 2023, v. 12, n. 15, p. 3331, doi. 10.3390/electronics12153331

By:

Ki, Donghan;
Lee, Minwoong;
Lee, Namho;
Cho, Seongik

Publication type:

Article

Design and Implementation of Low Power Multiplier Using Proposed Two Phase Clocked Adiabatic Static CMOS Logic Circuit.

Published in:

International Journal of Electrical & Computer Engineering (2088-8708), 2018, v. 8, n. 6, p. 4959, doi. 10.11591/ijece.v8i6.pp4959-4971

By:

Keote, Minal;
Karule, P. T.

Publication type:

Article

MINI Logic 1-Bit Adder: A Comparison with Hybrid NMOS-Memristor-Logic Styles Using Ta2O5/Al2O3 Based RRAM Device.

Published in:

Advances in Electrical & Computer Engineering, 2024, v. 24, n. 3, p. 33, doi. 10.4316/AECE.2024.03004

By:

NITHYA, Natarajan;
PARAMASIVAM, Kuppusamy

Publication type:

Article

PAELib: A VHDL Library for Area and Power Dissipation Estimation of CMOS Logic Circuits.

Published in:

Advances in Electrical & Computer Engineering, 2019, v. 19, n. 1, p. 9, doi. 10.4316/AECE.2019.01002

By:

KIREI, Botond Sandor;
CHEREJA, Verginia-Iulia-Maria;
HINTEA, Sorin;
TOPA, Marina Dana

Publication type:

Article

Modeling of Temperature-Dependent Noise in Silicon Nanowire FETs including Self-Heating Effects.

Published in:

Modelling & Simulation in Engineering, 2014, p. 1, doi. 10.1155/2014/635803

By:

Anandan, P.;
Malathi, N.;
Mohankumar, N.

Publication type:

Article

Clock Delayed Dual Keeper Semi Dynamic Inverter Domino Logic Circuit.

Published in:

Journal of Active & Passive Electronic Devices, 2020, v. 15, n. 1/2, p. 53

By:

DEO, MANISH;
KUMAR, MANISH

Publication type:

Article

N-Type Conjugated Polymer-Enabled Selective Dispersion of Semiconducting Carbon Nanotubes for Flexible CMOS-Like Circuits.

Published in:

Advanced Functional Materials, 2015, v. 25, n. 12, p. 1837, doi. 10.1002/adfm.201404126

By:

Wang, Huiliang;
Li, Yaoxuan;
Jiménez‐Osés, Gonzalo;
Liu, Peng;
Fang, Ya;
Zhang, Jie;
Lai, Ying‐Chih;
Park, Steve;
Chen, Liwei;
Houk, Kendall N.;
Bao, Zhenan

Publication type:

Article

Spin-Based Fully Nonvolatile Full-Adder Circuit for Computing in Memory.

Published in:

SPIN (2010-3247), 2019, v. 9, n. 1, p. N.PAG, doi. 10.1142/S2010324719500073

By:

Amirany, Abdolah;
Rajaei, Ramin

Publication type:

Article

Noise measurement in high-speed domino pseudo-CMOS keeper.

Published in:

Measurement & Control (0020-2940), 2019, v. 52, n. 1/2, p. 20, doi. 10.1177/0020294018813642

By:

Jaikumar, R.;
Poongodi, P.

Publication type:

Article

Automatic Crack Detection and Classification Method for Subway Tunnel Safety Monitoring.

Published in:

Sensors (14248220), 2014, v. 14, n. 10, p. 19307, doi. 10.3390/s141019307

By:

Wenyu Zhang;
Zhenjiang Zhang;
Dapeng Qi;
Yun Liu

Publication type:

Article

A Linearity-Enhanced Time-Domain CMOS Thermostat with Process-Variation Calibration.

Published in:

Sensors (14248220), 2014, v. 14, n. 10, p. 18784, doi. 10.3390/s141018784

By:

Chun-Chi Chen;
Yi Lin

Publication type:

Article

CMOS Readout Circuit Integrated with Ionizing Radiation Detectors.

Published in:

International Journal of Electronics & Telecommunications, 2014, v. 60, n. 1, p. 105, doi. 10.2478/eletel-2014-0014

By:

Szymański, Andrzej;
Obrębski, Dariusz;
Marczewski, Jacek;
Tomaszewski, Daniel;
Grodner, Mirosław;
Pieczyński, Janusz

Publication type:

Article

An efficient 70 GHz divide‐by‐4 CMOS frequency divider employing low threshold devices.

Published in:

Electronics Letters (Wiley-Blackwell), 2021, v. 57, n. 14, p. 545, doi. 10.1049/ell2.12171

By:

Tibenszky, Zoltán;
Carta, Corrado;
Ellinger, Frank

Publication type:

Article

High-performance and single event double-upset-immune latch design.

Published in:

Electronics Letters (Wiley-Blackwell), 2020, v. 56, n. 23, p. 1243, doi. 10.1049/el.2020.1823

By:

Zhang, Haineng;
Liu, Zhongyang;
Jiang, Jianwei;
Xiao, Jun;
Zhang, Zhengxuan;
Zou, Shichang

Publication type:

Article

Error-compensated time integrator in 28-nm CMOS technology.

Published in:

Electronics Letters (Wiley-Blackwell), 2020, v. 56, n. 16, p. 806, doi. 10.1049/el.2020.1074

By:

Ji, Xincun;
Wang, Youhua;
Shen, Mengqi;
Guo, Yufeng

Publication type:

Article

NVRH-LUT: A nonvolatile radiation-hardened hybrid MTJ/CMOS-based look-up table for ultralow power and highly reliable FPGA designs.

Published in:

Turkish Journal of Electrical Engineering & Computer Sciences, 2019, v. 27, n. 6, p. 4486, doi. 10.3906/elk-1812-179

By:

JAMSHIDI, Vahid

Publication type:

Article

A new CMOS logarithmic current generator.

Published in:

Turkish Journal of Electrical Engineering & Computer Sciences, 2016, v. 24, n. 5, p. 4517, doi. 10.3906/elk-1503-146

By:

AL-ABST, Munir;
AL-TAMIMI, Karama

Publication type:

Article

The Window Comparator Circuit with CMOS and TTL Logic ICs Switching levels.

Published in:

Przegląd Elektrotechniczny, 2024, v. 2024, n. 1, p. 112, doi. 10.15199/48.2024.01.23

By:

BOONKIRDRAM, Sarawoot;
SONASANG, Somchat;
SUMMATTA, Chuthong

Publication type:

Article

Performance Comparison of the Conventional CMOS and MTCMOS Digital Circuits and Their Simulation.

Published in:

International Review of Electrical Engineering, 2022, v. 17, n. 1, p. 66, doi. 10.15866/iree.v17i1.20555

By:

Zabeli, Milaim;
Hoxha, Betim

Publication type:

Article

Design of Memristor-Based Combinational Logic Circuits.

Published in:

Circuits, Systems & Signal Processing, 2021, v. 40, n. 12, p. 5825, doi. 10.1007/s00034-021-01770-1

By:

Liu, Gongzhi;
Shen, Shuhang;
Jin, Peipei;
Wang, Guangyi;
Liang, Yan

Publication type:

Article

Theory of Expansion Boolean Algebra and Its Applications in CMOS VLSI Digital Systems.

Published in:

Circuits, Systems & Signal Processing, 2019, v. 38, n. 12, p. 5817, doi. 10.1007/s00034-019-01163-5

By:

Jiang, En-hua;
Jiang, Wen-bin

Publication type:

Article

1 V Rectifier Based on Bulk-Driven Quasi-Floating-Gate Differential Difference Amplifiers.

Published in:

Circuits, Systems & Signal Processing, 2015, v. 34, n. 7, p. 2077, doi. 10.1007/s00034-014-9958-3

By:

Khateb, Fabian;
Vlassis, Spyridon;
Kumngern, Montree;
Psychalinos, Costas;
Kulej, Tomasz;
Vrba, Radimir;
Fujcik, Lukas

Publication type:

Article

A 1‐Gbps reference‐less burst‐mode CDR with embedded TDC in a 65‐nm CMOS process.

Published in:

International Journal of Circuit Theory & Applications, 2018, v. 46, n. 8, p. 1565, doi. 10.1002/cta.2490

By:

Wang, Yuan;
Jiang, Mengying;
Liu, Baoguang;
Jia, Song;
Zhang, Xing

Publication type:

Article