Clock gating methodologies and tools: a survey.
- Published in:
- International Journal of Circuit Theory & Applications, 2016, v. 44, n. 4, p. 798, doi. 10.1002/cta.2107
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- Publication type:
- Article
Works matching DE "CLOCK distribution networks"
Results: 8
1
2
In brief.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2019, v. 55, n. 5, p. 230, doi. 10.1049/el.2019.0554
- Publication type:
- Article
3
Hybrid interconnect network for on-chip low-power clock distribution.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2019, v. 55, n. 5, p. 244, doi. 10.1049/el.2018.6570
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- Publication type:
- Article
4
Design of Zero Skew Clock Tree for CMOS Image Sensor.
- Published in:
- IUP Journal of Electrical & Electronics Engineering, 2013, v. 6, n. 4, p. 7
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- Publication type:
- Article
5
Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits.
- Published in:
- Journal of Circuits, Systems & Computers, 2016, v. 25, n. 11, p. -1, doi. 10.1142/S0218126616501425
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- Publication type:
- Article
6
Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach.
- Published in:
- Journal of Multiple-Valued Logic & Soft Computing, 2014, v. 22, n. 1-2, p. 21
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- Publication type:
- Article
7
Accounting for Inter-System Bias in DGNSS Positioning with GPS/GLONASS/BDS/Galileo.
- Published in:
- Journal of Navigation, 2017, v. 70, n. 4, p. 686, doi. 10.1017/S0373463316000825
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- Publication type:
- Article
8
DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture.
- Published in:
- Technical Gazette / Tehnički Vjesnik, 2018, v. 25, n. 2, p. 358, doi. 10.17559/TV-20160802143634
- By:
- Publication type:
- Article