Works matching DE "CLOCK circuits (Electronics)"
Results: 7
MODIFIED DIVIDE BY 2/3 COUNTER DESIGN USING MTCMOS TECHNIQUES.
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- i-Manager's Journal on Electronics Engineering, 2013, v. 4, n. 2, p. 22
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- Article
Clock gating methodologies and tools: a survey.
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- International Journal of Circuit Theory & Applications, 2016, v. 44, n. 4, p. 798, doi. 10.1002/cta.2107
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- Article
2.5 mW 2.73 GHz non-overlapping multiphase clock generator with duty-cycle correction in 0.13 µm CMOS.
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- Electronics Letters (Wiley-Blackwell), 2016, v. 52, n. 14, p. 1261, doi. 10.1049/el.2016.1232
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- Article
Design of ternary clock generator.
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- Electronics Letters (Wiley-Blackwell), 2014, v. 50, n. 15, p. 1052, doi. 10.1049/el.2014.1590
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- Article
Excess Phase Noise Characterization in Multifrequency Remote Clock Distribution Based on Femtosecond Frequency Combs.
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- Applied Sciences (2076-3417), 2015, v. 5, n. 2, p. 77, doi. 10.3390/app5020077
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- Article
Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applications.
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- Australian Journal of Electrical & Electronic Engineering, 2018, v. 15, n. 3, p. 98, doi. 10.1080/1448837X.2018.1527101
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- Article
Maximum-Likelihood Estimator of Clock Offset between Nanomachines in Bionanosensor Networks.
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- Sensors (14248220), 2015, v. 15, n. 12, p. 30827, doi. 10.3390/s151229830
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- Article