Clock/Frequency Generation Circuits and Systems.
- Published in:
- Journal of Electrical & Computer Engineering, 2012, p. 1, doi. 10.1155/2012/941653
- By:
- Publication type:
- Article
Works matching DE "CLOCK %26 data recovery circuits"
Results: 11
1
2
Studies on Sensitivity of Clock and Data Recovery Circuits to Power Supply Noise.
- Published in:
- International Journal of Design, Analysis & Tools for Integrated Circuits & Systems, 2011, v. 1, n. 1, p. 16
- By:
- Publication type:
- Article
3
8-10 Gbit/s full synthesised continuous-half-rate reference-less all-digital CDR with sub-harmonic frequency extraction.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2018, v. 54, n. 20, p. 1156, doi. 10.1049/el.2018.6145
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- Publication type:
- Article
4
3.8 mW 10 Gbit/s CDR for intra-panel interface with a modulated training pattern.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2017, v. 53, n. 16, p. 1098, doi. 10.1049/el.2017.1726
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- Publication type:
- Article
5
Hardware-efficient phase-detection technique for digital clock and data recovery.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2013, v. 49, n. 1, p. 55, doi. 10.1049/el.2012.3722
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- Publication type:
- Article
6
A Low-Jitter Full-Rate 25-Gb/s CDR for 100-Gb/s Optical Interconnects in 0.13-μm SiGe BiCMOS.
- Published in:
- Fiber & Integrated Optics, 2017, v. 36, n. 4/5, p. 172, doi. 10.1080/01468030.2017.1364803
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- Publication type:
- Article
7
A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits.
- Published in:
- Circuits, Systems & Signal Processing, 2018, v. 37, n. 4, p. 1692, doi. 10.1007/s00034-017-0621-7
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- Publication type:
- Article
8
Phase Interpolator with Improved Linearity.
- Published in:
- Circuits, Systems & Signal Processing, 2016, v. 35, n. 2, p. 367, doi. 10.1007/s00034-015-0082-9
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- Publication type:
- Article
9
A 1‐Gbps reference‐less burst‐mode CDR with embedded TDC in a 65‐nm CMOS process.
- Published in:
- International Journal of Circuit Theory & Applications, 2018, v. 46, n. 8, p. 1565, doi. 10.1002/cta.2490
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- Publication type:
- Article
10
A 6-Gbps/lane receiver for a clock-forwarded link in 65-nm CMOS process.
- Published in:
- International Journal of Circuit Theory & Applications, 2015, v. 43, n. 4, p. 544, doi. 10.1002/cta.2080
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- Publication type:
- Article
11
A 1.7 Gbps DLL-Based Clock Data Recovery for a Serial Display Interface in 0.35-µm CMOS.
- Published in:
- ETRI Journal, 2012, v. 34, n. 1, p. 35, doi. 10.4218/etrij.11.0111.0143
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- Publication type:
- Article