Integrating backend processes.
- Published in:
- Solid State Technology, 2001, v. 44, n. 2, p. 78
- By:
- Publication type:
- Article
Works matching DE "CHIP scale packaging"
Results: 23
1
2
Modeling of moisture over-saturation and vapor pressure in die-attach film for stacked-die chip scale packages.
- Published in:
- Journal of Materials Science: Materials in Electronics, 2016, v. 27, n. 1, p. 481, doi. 10.1007/s10854-015-3778-5
- By:
- Publication type:
- Article
3
Effect of underfill on bending fatigue behavior of chip scale package.
- Published in:
- Journal of Materials Science: Materials in Electronics, 2008, v. 19, n. 5, p. 406, doi. 10.1007/s10854-007-9354-x
- By:
- Publication type:
- Article
4
Addressing Flux Dip Challenges for 3-D Integrated Large Die, Ultrafine Pitch Interconnect.
- Published in:
- Journal of Microelectronic & Electronic Packaging, 2017, v. 14, n. 1, p. 32, doi. 10.4071/imaps.348081
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- Publication type:
- Article
5
A genetic-based algorithm for the operational sequence of a high speed chip placement machine.
- Published in:
- International Journal of Advanced Manufacturing Technology, 2008, v. 36, n. 9/10, p. 918, doi. 10.1007/s00170-006-0918-3
- By:
- Publication type:
- Article
6
Materials Technologies for Thermomechanical Management of Organic Packages.
- Published in:
- Intel Technology Journal, 2005, v. 9, n. 4, p. 309, doi. 10.1535/itj.0904.05
- By:
- Publication type:
- Article
7
A LOW-PHASE-NOISE CMOS VCO FOR K-BAND APPLICATION.
- Published in:
- Journal of Circuits, Systems & Computers, 2013, v. 22, n. 6, p. -1, doi. 10.1142/S0218126613500400
- By:
- Publication type:
- Article
8
Mechanical strength of chip scale package with various underfills under accelerated thermal condition.
- Published in:
- Materials Science & Technology, 2007, v. 23, n. 7, p. 828, doi. 10.1179/174328407X192750
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- Publication type:
- Article
9
Energy-Aware Modeling of Scaled Heterogeneous Systems.
- Published in:
- International Journal of Parallel Programming, 2017, v. 45, n. 5, p. 1026, doi. 10.1007/s10766-016-0453-2
- By:
- Publication type:
- Article
10
Numerical analysis on thermal characteristics for chip scale package by integrating 2D/3D models.
- Published in:
- International Journal of Numerical Modelling, 2009, v. 22, n. 1, p. 43, doi. 10.1002/jnm.694
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- Publication type:
- Article
11
Using a diffusion wavelet neural network for short-term time series learning in the wafer level chip scale package process.
- Published in:
- Journal of Intelligent Manufacturing, 2016, v. 27, n. 6, p. 1261, doi. 10.1007/s10845-014-0949-9
- By:
- Publication type:
- Article
12
INTEGRATED PASSIVE AND ACTIVE DEVICES USING CSP, DFN AND QFN PACKAGING FOR PORTABLE ELECTRONIC APPLICATIONS.
- Published in:
- Microwave Journal, 2006, v. 49, n. 2, p. 138
- By:
- Publication type:
- Article
13
Coupled Integration of CSAC, MIMU, and GNSS for Improved PNT Performance.
- Published in:
- Sensors (14248220), 2016, v. 16, n. 5, p. 682, doi. 10.3390/s16050682
- By:
- Publication type:
- Article
14
The Effects of Additives to SnAgCu Alloys on Microstructure and Drop Impact of Reliability of Solder Joints.
- Published in:
- JOM: The Journal of The Minerals, Metals & Materials Society (TMS), 2007, v. 59, n. 7, p. 26, doi. 10.1007/s11837-007-0085-5
- By:
- Publication type:
- Article
15
The Observation and Simulation of Sn-Ag-Cu Solder Solidification in Chip-Scale Packaging.
- Published in:
- JOM: The Journal of The Minerals, Metals & Materials Society (TMS), 2004, v. 56, n. 6, p. 39, doi. 10.1007/s11837-004-0109-3
- By:
- Publication type:
- Article
16
Pixel-to-Pixel Correspondence Adjustment in DMD Camera by Moiré Methodology.
- Published in:
- Experimental Mechanics, 2006, v. 46, n. 1, p. 67, doi. 10.1007/s11340-006-5861-6
- By:
- Publication type:
- Article
17
Failure Analysis Challenges for Chip-Scale Packages.
- Published in:
- Electronic Device Failure Analysis, 2013, v. 15, n. 2, p. 14, doi. 10.31399/asm.edfa.2013-2.p014
- By:
- Publication type:
- Article
18
Life cycle assessment of integrated circuit packaging technologies.
- Published in:
- International Journal of Life Cycle Assessment, 2011, v. 16, n. 3, p. 258, doi. 10.1007/s11367-011-0260-3
- By:
- Publication type:
- Article
19
Study of the Au/In Reaction for Transient Liquid-Phase Bonding and 3D Chip Stacking.
- Published in:
- Journal of Electronic Materials, 2008, v. 37, n. 8, p. 1095, doi. 10.1007/s11664-008-0487-3
- By:
- Publication type:
- Article
20
Effect of Thermal Aging on Drop Performance of Chip Scale Packages with SnAgCu Solder Joints on Cu Pads.
- Published in:
- Journal of Electronic Materials, 2007, v. 36, n. 12, p. 1679, doi. 10.1007/s11664-007-0260-z
- By:
- Publication type:
- Article
21
Failure Mechanisms of Lead-Free Chip Scale Package Interconnections under Fast Mechanical Loading.
- Published in:
- Journal of Electronic Materials, 2005, v. 34, n. 7, p. 969, doi. 10.1007/s11664-005-0084-7
- By:
- Publication type:
- Article
22
Influence of Interfacial Reaction Layer on Reliability of Chip-Scale Package Joint from Using Sn-37Pb and Sn-8Zn-3Bi Solder.
- Published in:
- Journal of Electronic Materials, 2005, v. 34, n. 2, p. 161, doi. 10.1007/s11664-005-0228-9
- By:
- Publication type:
- Article
23
THERMAL CHARACTERIZATION OF THERMAL INTERFACE MATERIALS.
- Published in:
- Experimental Techniques, 2008, v. 32, n. 3, p. 48, doi. 10.1111/j.1747-1567.2007.00212.x
- By:
- Publication type:
- Article