Works matching DE "BUILT-in self tests (Engineering)"
Results: 16
New test points help contain growing test costs.
- Published in:
- EE: Evaluation Engineering, 2017, v. 56, n. 11, p. 16
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- Article
A Flexible Programmable Memory BIST for Embedded Single-Port Memory and Dual-Port Memory.
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- ETRI Journal, 2013, v. 35, n. 5, p. 808, doi. 10.4218/etrij.13.0112.0717
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- Article
Novel Architecture for Logic Test Using Single Cycle Access Structure.
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- Journal of VLSI Circuits & Systems (JVCS), 2021, v. 3, n. 1, p. 1, doi. 10.31838/jvcs/03.01.01
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- Article
A Precise Design for Testing High-Speed Embedded Memory using a BIST Circuit.
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- IETE Journal of Research, 2017, v. 63, n. 4, p. 473, doi. 10.1080/03772063.2017.1285259
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- Article
Editorial.
- Published in:
- 2014
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- Publication type:
- Editorial
Low Power Memory Built in Self Test Address Generator Using Clock Controlled Linear Feedback Shift Registers.
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- Journal of Electronic Testing, 2014, v. 30, n. 1, p. 77, doi. 10.1007/s10836-014-5432-1
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- Article
A low-cost DAC BIST structure using a resistor loop.
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- PLoS ONE, 2017, v. 12, n. 2, p. 1, doi. 10.1371/journal.pone.0172331
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- Article
An Analog-Digital Mixed Measurement Method of Inductive Proximity Sensor.
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- Sensors (14248220), 2016, v. 16, n. 1, p. 30, doi. 10.3390/s16010030
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- Publication type:
- Article
Embryonic Architecture with Built-in Self-test and GA Evolved Configuration Data.
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- International Journal of Electronics & Telecommunications, 2023, v. 69, n. 2, p. 211, doi. 10.24425/ijet.2023.144352
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- Publication type:
- Article
Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs.
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- Journal of Cellular Automata, 2017, v. 12, n. 3/4, p. 217
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- Publication type:
- Article
Oscillation-Based DFT for Second-Order Bandpass OTA-C Filters.
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- Circuits, Systems & Signal Processing, 2018, v. 37, n. 5, p. 1807, doi. 10.1007/s00034-017-0648-9
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- Publication type:
- Article
An Access Mechanism for Embedded Sensors in Modern SoCs.
- Published in:
- Journal of Electronic Testing, 2017, v. 33, n. 4, p. 397, doi. 10.1007/s10836-017-5669-6
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- Publication type:
- Article
Editorial.
- Published in:
- 2016
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- Publication type:
- Editorial
A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis.
- Published in:
- Journal of Electronic Testing, 2015, v. 31, n. 2, p. 207, doi. 10.1007/s10836-015-5515-7
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- Publication type:
- Article
Optimization Design of Weighted Built-In Self-Test based on Multi-Objective Genetic Algorithm.
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- International Journal of Simulation: Systems, Science & Technology, 2016, v. 17, n. 2, p. 12.1, doi. 10.5013/IJSSST.a.17.02.12
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- Publication type:
- Article
An Efficient SIC Generator using X Filling Techniques for Low Power Scan based BIST.
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- International Journal of Simulation: Systems, Science & Technology, 2017, v. 18, n. 2, p. 10.1, doi. 10.5013/IJSSST.a.18.02.10
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- Publication type:
- Article