Works matching DE "BUILT-in self tests (Engineering)"

Results: 16

Optimization Design of Weighted Built-In Self-Test based on Multi-Objective Genetic Algorithm.

Published in:

International Journal of Simulation: Systems, Science & Technology, 2016, v. 17, n. 2, p. 12.1, doi. 10.5013/IJSSST.a.17.02.12

By:

Zhao Peng;
Jing Hongli

Publication type:

Article

An Access Mechanism for Embedded Sensors in Modern SoCs.

Published in:

Journal of Electronic Testing, 2017, v. 33, n. 4, p. 397, doi. 10.1007/s10836-017-5669-6

By:

He, Miao;
Tehranipoor, Mark

Publication type:

Article

Editorial.

Published in:

2016

By:

Agrawal, Vishwani

Publication type:

Editorial

A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis.

Published in:

Journal of Electronic Testing, 2015, v. 31, n. 2, p. 207, doi. 10.1007/s10836-015-5515-7

By:

Pereira, Igor;
Dias, Leonardo;
Souza, Cleonilson

Publication type:

Article

Editorial.

Published in:

2014

By:

Agrawal, Vishwani

Publication type:

Editorial

Low Power Memory Built in Self Test Address Generator Using Clock Controlled Linear Feedback Shift Registers.

Published in:

Journal of Electronic Testing, 2014, v. 30, n. 1, p. 77, doi. 10.1007/s10836-014-5432-1

By:

Krishna, K.;
Sailaja, M.

Publication type:

Article

New test points help contain growing test costs.

Published in:

EE: Evaluation Engineering, 2017, v. 56, n. 11, p. 16

By:

Mayer, Jeff

Publication type:

Article

A Precise Design for Testing High-Speed Embedded Memory using a BIST Circuit.

Published in:

IETE Journal of Research, 2017, v. 63, n. 4, p. 473, doi. 10.1080/03772063.2017.1285259

By:

Zhang, Lijun;
Wang, Ziou;
Li, Youzhong;
Mao, Lingfeng

Publication type:

Article

A low-cost DAC BIST structure using a resistor loop.

Published in:

PLoS ONE, 2017, v. 12, n. 2, p. 1, doi. 10.1371/journal.pone.0172331

By:

Jang, Jaewon;
Kim, Heetae;
Kang, Sungho

Publication type:

Article

An Analog-Digital Mixed Measurement Method of Inductive Proximity Sensor.

Published in:

Sensors (14248220), 2016, v. 16, n. 1, p. 30, doi. 10.3390/s16010030

By:

Yi-Xin Guo;
Zhi-Biao Shao;
Ting Li

Publication type:

Article

Embryonic Architecture with Built-in Self-test and GA Evolved Configuration Data.

Published in:

International Journal of Electronics & Telecommunications, 2023, v. 69, n. 2, p. 211, doi. 10.24425/ijet.2023.144352

By:

Malhotra, Gayatri;
Duraiswamy, Punithavathi;
Kishore, J. K.

Publication type:

Article

Novel Architecture for Logic Test Using Single Cycle Access Structure.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2021, v. 3, n. 1, p. 1, doi. 10.31838/jvcs/03.01.01

By:

PITTALA, CHANDRA SHAKER;
SRAVANA, J.;
AJITHA, G.;
LAKSHAMANACHARI, S.;
VIJAY, V.;
VENKATESWARLU, S. CHINA

Publication type:

Article

Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs.

Published in:

Journal of Cellular Automata, 2017, v. 12, n. 3/4, p. 217

By:

PALCHAUDHURI, AYAN;
AMRESH, AMRIT ANAND;
DHAR, ANINDYA SUNDAR

Publication type:

Article

Oscillation-Based DFT for Second-Order Bandpass OTA-C Filters.

Published in:

Circuits, Systems & Signal Processing, 2018, v. 37, n. 5, p. 1807, doi. 10.1007/s00034-017-0648-9

By:

Hasan, Masood-ul;
Zhu, Yanqing;
Sun, Yichuang

Publication type:

Article

An Efficient SIC Generator using X Filling Techniques for Low Power Scan based BIST.

Published in:

International Journal of Simulation: Systems, Science & Technology, 2017, v. 18, n. 2, p. 10.1, doi. 10.5013/IJSSST.a.18.02.10

By:

Hussain, Sabir;
Rao, V. Malleshwara

Publication type:

Article

A Flexible Programmable Memory BIST for Embedded Single-Port Memory and Dual-Port Memory.

Published in:

ETRI Journal, 2013, v. 35, n. 5, p. 808, doi. 10.4218/etrij.13.0112.0717

By:

Youngkyu Park;
Hong-Sik Kim;
Inhyuk Choi;
Sungho Kang

Publication type:

Article