Works matching DE "ADDERS (Digital electronics)"

Results: 81

Fast arithmetic in algorithmic self-assembly.

Published in:

Natural Computing, 2016, v. 15, n. 1, p. 115, doi. 10.1007/s11047-015-9512-7

By:

Keenan, Alexandra;
Schweller, Robert;
Sherman, Michael;
Zhong, Xingsi

Publication type:

Article

Adaptive estimation of variable weights in a linear adder.

Published in:

Automation & Remote Control, 2013, v. 74, n. 4, p. 660, doi. 10.1134/S0005117913040085

By:

Ovcharenko, V.

Publication type:

Article

Novel, low-supply, differential XOR/XNOR with rail-to-rail swing, for hamming-code generation.

Published in:

International Journal of Electronics Letters, 2018, v. 6, n. 3, p. 272, doi. 10.1080/21681724.2017.1357761

By:

Sarada, Musala;
Srinivasulu, Avireni;
Pal, Dipankar

Publication type:

Article

A Novel Design of an Ultra Low Voltage Energy-Efficient Full Adder.

Published in:

IUP Journal of Telecommunications, 2014, v. 6, n. 3, p. 53

By:

Manisha;
Archana Kumari, A. P.

Publication type:

Article

4-bit Brent Kung Parallel Prefix Adder Simulation Study Using Silvaco EDA Tools.

Published in:

International Journal of Simulation: Systems, Science & Technology, 2012, v. 13, n. 3A, p. 51

By:

Abidin, Anas Zainal;
Mutalib Al Junid, Syed Abdul;
Mohd Sharif, Khairul Khaizi;
Othman, Zulkifli;
Haron, Muhammad Adib

Publication type:

Article

Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints.

Published in:

Journal of Electronic Testing, 2018, v. 34, n. 1, p. 7, doi. 10.1007/s10836-017-5701-x

By:

Salehi, Mostafa;
Azarpeyvand, Ali;
Aboutalebi, Armin Hajaboutalebi

Publication type:

Article

A Study on 2D 2-Dot 1-Electron QCA Based Full Adder and Ripple Carry Adder Design.

Published in:

Nanosistemi, Nanomateriali, Nanotehnologii, 2018, v. 16, n. 2, p. 289

By:

Md. Abdullah-Al-Shafi

Publication type:

Article

Low Power and Area Efficient 2C Multiply-Accumulate Unit and Its Application to a DTMAC Unit.

Published in:

International Journal of Advanced Research in Computer Science, 2012, v. 3, n. 6, p. 45

By:

Vimal Raj, V.;
Manikandababu, C. S.

Publication type:

Article

Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder.

Published in:

Computer Systems Science & Engineering, 2023, v. 46, n. 1, p. 2659, doi. 10.32604/csse.2023.025075

By:

Annapoorani, B.;
Marikkannu, P.

Publication type:

Article

Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder.

Published in:

Computer Systems Science & Engineering, 2023, v. 45, n. 3, p. 2659, doi. 10.32604/csse.2023.025075

By:

Annapoorani, B.;
Marikkannu, P.

Publication type:

Article

Turbo coding for the noisy 2-user binary adder channel with punctured convolutional codes.

Published in:

Telecommunication Systems, 2017, v. 64, n. 3, p. 459, doi. 10.1007/s11235-016-0185-z

By:

Alcoforado, Maria;
Jesus, Jamerson;
Rocha, Valdemar

Publication type:

Article

A Fault Tolerant Adder Based On Alternative Computation.

Published in:

International Journal of Design, Analysis & Tools for Integrated Circuits & Systems, 2012, v. 3, n. 1, p. 14

By:

Khedhiri, Chiraz;
Karmani, Mouna;
Hamdi, Belgacem;
Man, Ka Lok

Publication type:

Article

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing.

Published in:

International Journal of Theoretical Physics, 2018, v. 57, n. 5, p. 1356, doi. 10.1007/s10773-018-3664-z

By:

Bilal, Bisma;
Ahmed, Suhaib;
Kakkar, Vipan

Publication type:

Article

A Three-Layer Full Adder/Subtractor Structure in Quantum-Dot Cellular Automata.

Published in:

International Journal of Theoretical Physics, 2017, v. 56, n. 9, p. 2848, doi. 10.1007/s10773-017-3453-0

By:

Barughi, Yashar;
Heikalabad, Saeed

Publication type:

Article

On Design of Parity Preserving Reversible Adder Circuits.

Published in:

International Journal of Theoretical Physics, 2016, v. 55, n. 12, p. 5118, doi. 10.1007/s10773-016-3133-5

By:

Haghparast, Majid;
Bolhassani, Ali

Publication type:

Article

Limited Carry-Propagate Multiply-Accumulate Unit Design for Reconfigurable Systems.

Published in:

Electronics & Electrical Engineering, 2017, v. 23, n. 2, p. 36, doi. 10.5755/j01.eie.23.2.17997

By:

Cini, Ugur;
Kocyigit, Gokhan

Publication type:

Article

Fully pipelined CORDIC-based inverse kinematic FPGA design for biped robots.

Published in:

Electronics Letters (Wiley-Blackwell), 2015, v. 51, n. 16, p. 1241, doi. 10.1049/el.2015.1604

By:

Rih-Lung Chung;
Yi-Qin Zhang;
Shih-Lun Chen

Publication type:

Article

Area efficient floating-point FFT butterfly architectures based on multi-operand adders.

Published in:

Electronics Letters (Wiley-Blackwell), 2015, v. 51, n. 12, p. 895, doi. 10.1049/el.2015.0342

By:

Kaivani, Amir;
Seok-Bum Ko

Publication type:

Article

Unified architecture for 2, 3, 4, 5, and 7-point DFTs based on Winograd Fourier transform algorithm.

Published in:

Electronics Letters (Wiley-Blackwell), 2013, v. 49, n. 5, p. 1, doi. 10.1049/el.2012.0577

By:

Qureshi, F.;
Garrido, M.;
Gustafsson, O.

Publication type:

Article

Two Low Power and High Efficient Full Adder Cells Based on CNTFET Technology.

Published in:

International Journal of Nanoelectronics & Materials, 2018, v. 11, n. 3, p. 321

By:

Farahani, Masoud;
Moradi, Mona

Publication type:

Article

High Performance CNFET-based Ternary Full Adders.

Published in:

IETE Journal of Research, 2018, v. 64, n. 1, p. 108, doi. 10.1080/03772063.2017.1338973

By:

Sharifi, Fazel;
Panahi, Atiyeh;
Moaiyeri, Mohammad Hossein;
Sharifi, Hojjat;
Navi, Keivan

Publication type:

Article

A Physics-Based Model of Double-Gate Tunnel FET for Circuit Simulation.

Published in:

IETE Journal of Research, 2016, v. 62, n. 3, p. 387, doi. 10.1080/03772063.2015.1082443

By:

Narendiran, A.;
Akhila, K.;
Bindu, B.

Publication type:

Article

Low-Power Modified Shift-Add Multiplier Design Using Parallel Prefix Adder.

Published in:

Journal of Circuits, Systems & Computers, 2019, v. 28, n. 2, p. N.PAG, doi. 10.1142/S0218126619500191

By:

Pinto, Rohan;
Shama, Kumara

Publication type:

Article

A 0.6V 19.5W 80dB DR Modulator with SA-Quantizers and Digital Feedforward Path.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 7, p. -1, doi. 10.1142/S0218126617501171

By:

Chen, Hongmei;
Wang, Li;
Li, Ting;
He, Lin;
Lin, Fujiang

Publication type:

Article

Design and Implementation of 32-Bit High Valency Jackson Adders.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 7, p. -1, doi. 10.1142/S0218126617501237

By:

Poornima, N.;
Bhaaskaran, V. S. Kanchana

Publication type:

Article

A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500827

By:

Mehrabani, Yavar Safaei;
Mirzaee, Reza Faghih;
Zareei, Zahra;
Daryabari, Seyedeh Mohtaram

Publication type:

Article

An Energy Efficient Logic Approach to Implement CMOS Full Adder.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500840

By:

Kumar, Pankaj;
Sharma, Rajender Kumar

Publication type:

Article

Efficient Realization of Fixed-Point Binary and Ternary Adders on FPGAs.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 4, p. -1, doi. 10.1142/S0218126617500530

By:

Khurshid, Burhan;
Naaz, Roohie

Publication type:

Article

Multistage Latency Adders Architecture Employing Approximate Computing.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 3, p. -1, doi. 10.1142/S0218126617500396

By:

Yang, Xinghua;
Xing, Yue;
Qiao, Fei;
Yang, Huazhong

Publication type:

Article

Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 1, p. 1, doi. 10.1142/S0218126617500141

By:

Parameshwara, M. C.;
Srinivasaiah, H. C.

Publication type:

Article

Modified Operand Decomposition Multiplication for High Performance Parallel Multipliers.

Published in:

Journal of Circuits, Systems & Computers, 2016, v. 25, n. 12, p. -1, doi. 10.1142/S0218126616501498

By:

Abid, Z.;
El-Dib, Dalia A.;
Mudassir, Rizwan

Publication type:

Article

A Low-Power and Area-Efficient 64-Bit Digital Comparator.

Published in:

Journal of Circuits, Systems & Computers, 2016, v. 25, n. 12, p. -1, doi. 10.1142/S0218126616501486

By:

Vijaya Krishna Boppana, N. V.;
Ren, Saiyu

Publication type:

Article

Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic.

Published in:

Journal of Circuits, Systems & Computers, 2016, v. 25, n. 7, p. -1, doi. 10.1142/S0218126616500730

By:

Singhal, Subodh Kumar;
Mohanty, Basant Kumar

Publication type:

Article

Efficient Audio Filter Using Folded Pipelining Architecture Based on Retiming Using Evolutionary Computation.

Published in:

Journal of Circuits, Systems & Computers, 2015, v. 24, n. 5, p. -1, doi. 10.1142/S0218126615500681

By:

Yagain, Deepa;
Balla, Sivanag;
Krishna, Vijaya

Publication type:

Article

SELF-TIMED SECTION-CARRY BASED CARRY LOOKAHEAD ADDERS AND THE CONCEPT OF ALIAS LOGIC.

Published in:

Journal of Circuits, Systems & Computers, 2013, v. 22, n. 4, p. 1, doi. 10.1142/S021812661350028X

By:

BALASUBRAMANIAN, P.;
EDWARDS, D. A.;
TOMS1, W. B.

Publication type:

Article

MULTIFUNCTION RNS MODULO 2<sup>n</sup> ± 1 MULTIPLIERS.

Published in:

Journal of Circuits, Systems & Computers, 2012, v. 21, n. 4, p. -1, doi. 10.1142/S0218126612500272

By:

JUANG, TSO-BING;
KUO, CHAO-TSUNG;
WU, GO-LONG;
HUANG, JIAN-HAO

Publication type:

Article

Comments on: Optical computation based on nonlinear total reflectional optical switch at the interface.

Published in:

Pramana: Journal of Physics, 2015, v. 85, n. 6, p. 1257, doi. 10.1007/s12043-015-0949-0

By:

ZAGHLOUL, Y

Publication type:

Article

DESIGN OF LOW POWER 14T FULL ADDER CELL USING DOUBLE GATE MOSFET WITH MTCMOS REDUCTION TECHNIQUE AT 45 NANOMETER TECHNOLOGY.

Published in:

International Journal of Nanoscience, 2013, v. 12, n. 6, p. -1, doi. 10.1142/S0219581X13500427

By:

SHRIVASTAVA, ANUJ KUMAR;
AKASHE, SHYAM

Publication type:

Article

Novel designs of full adder in quantum-dot cellular automata technology.

Published in:

Journal of Supercomputing, 2018, v. 74, n. 9, p. 4798, doi. 10.1007/s11227-018-2481-8

By:

Wang, Lei;
Xie, Guangjun

Publication type:

Article

Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic.

Published in:

Electronics (2079-9292), 2018, v. 7, n. 10, p. 243, doi. 10.3390/electronics7100243

By:

Balasubramanian, Padmanabhan;
Maskell, Douglas;
Mastorakis, Nikos

Publication type:

Article

Comparative Analysis of 8-Bit Adder Cells Using CLRCL Full Adder Logic.

Published in:

GSTF Journal on Computing, 2014, v. 3, n. 4, p. 104, doi. 10.7603/s40601-013-0046-5

By:

Kumar, Keshav;
Grover, Amit;
Grover, Neeti

Publication type:

Article

Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA.

Published in:

International Journal of Electrical & Computer Engineering (2088-8708), 2016, v. 6, n. 3, p. 1205, doi. 10.11591/ijece.v6i3.9457

By:

Bhavani, M.;
Kumar, M. Siva;
Rao, K. Srinivas

Publication type:

Article

Alternative Approach of Developing Optical Binary Adder Using Reversible Peres Gates.

Published in:

International Journal of Optics, 2018, p. 1, doi. 10.1155/2018/8541371

By:

Mandal, Dhoumendra;
Mandal, Sumana;
Mandal, Mrinal Kanti;
Garai, Sisir Kumar

Publication type:

Article

DEDICATED HARDWARE FOR COMPLEX MATHEMATICAL OPERATIONS.

Published in:

Computing & Informatics, 2016, v. 35, n. 6, p. 1438

By:

MALÍK, Peter

Publication type:

Article

Implementing a one-bit reversible full adder using quantum-dot cellular automata.

Published in:

Quantum Information Processing, 2014, v. 13, n. 9, p. 2127, doi. 10.1007/s11128-014-0782-2

By:

Mohammadi, Zahra;
Mohammadi, Majid

Publication type:

Article

Low Cost FPGA Implementation of RFIR Filter Based on a Radix-4 Algorithm.

Published in:

International Journal of Intelligent Engineering & Systems, 2018, v. 11, n. 5, p. 331, doi. 10.22266/ijies2018.1031.30

By:

Venkateswarlu, Chetti;
Kumar, Tipparti Anil

Publication type:

Article

A Low Power VLSI Implementation of Reconfigurable FIR Filter Using Carry Bypass Adder.

Published in:

International Journal of Intelligent Engineering & Systems, 2018, v. 11, n. 2, p. 225, doi. 10.22266/ijies2018.0430.25

By:

Reddy, Kasarla Satish;
Suresh, Hosahally Narayangowda

Publication type:

Article

Principle and design of ternary optical accumulator implementing M-k-B addition.

Published in:

Optical Engineering, 2014, v. 53, n. 9, p. 1, doi. 10.1117/1.OE.53.9.095108

By:

Yunfu Shen;
Benpeng Jiang;
Yi Jin;
Ouyang Shan;
Junjie Peng

Publication type:

Article

High Performance DIF-FFT Using Dissimilar Partitioned LUT Based Distributed Arithmetic.

Published in:

International Journal of Electronics & Telecommunications, 2021, v. 67, n. 4, p. 631, doi. 10.24425/ijet.2021.137856

By:

Cheepurupalli, Kusma Kumari;
Charan, Muntha;
Rao, Jammu Bhaskara;
Noor, Mahammad S.

Publication type:

Article

Design And Analysis Of 1-Bit Full Adder Using Cntfets.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2020, v. 2, n. 1, p. 14, doi. 10.31838/jvcs/02.01.04

By:

J., MURALIDHARAN

Publication type:

Article