Works matching DE "ADDERS (Digital electronics)"
Results: 81
Fast arithmetic in algorithmic self-assembly.
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- Natural Computing, 2016, v. 15, n. 1, p. 115, doi. 10.1007/s11047-015-9512-7
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- Article
Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2016, v. 6, n. 3, p. 1205, doi. 10.11591/ijece.v6i3.9457
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- Article
Formal Analysis of Hybrid Prefix/Carry-Select Arithmetic Systems.
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- Computer Journal, 2011, v. 54, n. 6, p. 894, doi. 10.1093/comjnl/bxq048
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- Article
Design of novel efficient adder and subtractor for quantum-dot cellular automata.
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- International Journal of Circuit Theory & Applications, 2015, v. 43, n. 10, p. 1446, doi. 10.1002/cta.2019
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- Article
A framework for high-speed parallel-prefix adder performance evaluation and comparison.
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- International Journal of Circuit Theory & Applications, 2015, v. 43, n. 10, p. 1474, doi. 10.1002/cta.2020
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- Article
Simplified carry save adder-based array multiplier scheme and circuits design.
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- International Journal of Circuit Theory & Applications, 2015, v. 43, n. 9, p. 1226, doi. 10.1002/cta.1998
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- Article
Design of high-speed low-power parallel-prefix adder trees in nanometer technologies.
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- International Journal of Circuit Theory & Applications, 2014, v. 42, n. 7, p. 731, doi. 10.1002/cta.1886
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- Article
Turbo coding for the noisy 2-user binary adder channel with punctured convolutional codes.
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- Telecommunication Systems, 2017, v. 64, n. 3, p. 459, doi. 10.1007/s11235-016-0185-z
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- Article
DESIGN OF LOW POWER 14T FULL ADDER CELL USING DOUBLE GATE MOSFET WITH MTCMOS REDUCTION TECHNIQUE AT 45 NANOMETER TECHNOLOGY.
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- International Journal of Nanoscience, 2013, v. 12, n. 6, p. -1, doi. 10.1142/S0219581X13500427
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- Article
Design And Analysis Of 1-Bit Full Adder Using Cntfets.
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- Journal of VLSI Circuits & Systems (JVCS), 2020, v. 2, n. 1, p. 14, doi. 10.31838/jvcs/02.01.04
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- Article
Energy Efficient and Low Power Rca Based Full Adder.
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- Journal of VLSI Circuits & Systems (JVCS), 2020, v. 2, n. 1, p. 6, doi. 10.31838/jvcs/02.01.02
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- Article
High Performance CNFET-based Ternary Full Adders.
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- IETE Journal of Research, 2018, v. 64, n. 1, p. 108, doi. 10.1080/03772063.2017.1338973
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- Article
A Physics-Based Model of Double-Gate Tunnel FET for Circuit Simulation.
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- IETE Journal of Research, 2016, v. 62, n. 3, p. 387, doi. 10.1080/03772063.2015.1082443
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- Article
Binary Implementation of Parallel Ternary Full Adder and Subtractor.
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- International Review on Computers & Software, 2012, v. 7, n. 2, p. 495
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- Article
Novel designs of full adder in quantum-dot cellular automata technology.
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- Journal of Supercomputing, 2018, v. 74, n. 9, p. 4798, doi. 10.1007/s11227-018-2481-8
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- Article
An optimized embedded adder for digital signal processing applications.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2016, v. 24, n. 6, p. 5224, doi. 10.3906/elk-1412-140
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- Article
DEDICATED HARDWARE FOR COMPLEX MATHEMATICAL OPERATIONS.
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- Computing & Informatics, 2016, v. 35, n. 6, p. 1438
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- Article
Comments on: Optical computation based on nonlinear total reflectional optical switch at the interface.
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- Pramana: Journal of Physics, 2015, v. 85, n. 6, p. 1257, doi. 10.1007/s12043-015-0949-0
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- Article
Adaptive estimation of variable weights in a linear adder.
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- Automation & Remote Control, 2013, v. 74, n. 4, p. 660, doi. 10.1134/S0005117913040085
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- Article
An Architecture of 2-Dimensional 4-Dot 2-Electron QCA Full Adder and Subtractor with Energy Dissipation Study.
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- Active & Passive Electronic Components, 2018, p. 1, doi. 10.1155/2018/5062960
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- Article
Low Power and Area Efficient 2C Multiply-Accumulate Unit and Its Application to a DTMAC Unit.
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- International Journal of Advanced Research in Computer Science, 2012, v. 3, n. 6, p. 45
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- Article
Limited Carry-Propagate Multiply-Accumulate Unit Design for Reconfigurable Systems.
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- Electronics & Electrical Engineering, 2017, v. 23, n. 2, p. 36, doi. 10.5755/j01.eie.23.2.17997
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- Article
Fully pipelined CORDIC-based inverse kinematic FPGA design for biped robots.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2015, v. 51, n. 16, p. 1241, doi. 10.1049/el.2015.1604
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- Article
Area efficient floating-point FFT butterfly architectures based on multi-operand adders.
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- Electronics Letters (Wiley-Blackwell), 2015, v. 51, n. 12, p. 895, doi. 10.1049/el.2015.0342
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- Article
Unified architecture for 2, 3, 4, 5, and 7-point DFTs based on Winograd Fourier transform algorithm.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2013, v. 49, n. 5, p. 1, doi. 10.1049/el.2012.0577
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- Article
PERFORMANCE ANALYSIS OF ADDER CIRCUITS USING FINFET'S.
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- i-Manager's Journal on Circuits & Systems, 2017, v. 5, n. 3, p. 1, doi. 10.26634/jcir.5.3.13811
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- Article
High Performance DIF-FFT Using Dissimilar Partitioned LUT Based Distributed Arithmetic.
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- International Journal of Electronics & Telecommunications, 2021, v. 67, n. 4, p. 631, doi. 10.24425/ijet.2021.137856
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- Article
A MODIFIED PARTIAL PRODUCT GENERATOR FOR BINARY MULTIPLIERS USING DIFFERENT ADDERS.
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- i-Manager's Journal on Electronics Engineering, 2016, v. 6, n. 3, p. 21, doi. 10.26634/jele.6.3.5956
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- Article
DESIGN OF FIR FILTER FOR EFFICIENT FPGA IMPLEMENTATION.
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- i-Manager's Journal on Electronics Engineering, 2015, v. 5, n. 3, p. 1, doi. 10.26634/jele.5.3.3392
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- Article
DESIGN OF RIPPLE CARRY ADDER USING CONSTANT DELAY.
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- i-Manager's Journal on Electronics Engineering, 2014, v. 4, n. 3, p. 29, doi. 10.26634/jele.4.3.2678
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- Article
SPEED COMPARISON OF THE ADDERS IN FPGA.
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- Science & Military Journal, 2013, v. 8, n. 1, p. 18
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- Article
Low-Power Modified Shift-Add Multiplier Design Using Parallel Prefix Adder.
- Published in:
- Journal of Circuits, Systems & Computers, 2019, v. 28, n. 2, p. N.PAG, doi. 10.1142/S0218126619500191
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- Article
A 0.6V 19.5W 80dB DR Modulator with SA-Quantizers and Digital Feedforward Path.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 7, p. -1, doi. 10.1142/S0218126617501171
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- Article
Design and Implementation of 32-Bit High Valency Jackson Adders.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 7, p. -1, doi. 10.1142/S0218126617501237
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- Article
A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500827
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- Article
An Energy Efficient Logic Approach to Implement CMOS Full Adder.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500840
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- Article
Efficient Realization of Fixed-Point Binary and Ternary Adders on FPGAs.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 4, p. -1, doi. 10.1142/S0218126617500530
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- Article
Multistage Latency Adders Architecture Employing Approximate Computing.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 3, p. -1, doi. 10.1142/S0218126617500396
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- Publication type:
- Article
Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 1, p. 1, doi. 10.1142/S0218126617500141
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- Article
Modified Operand Decomposition Multiplication for High Performance Parallel Multipliers.
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- Journal of Circuits, Systems & Computers, 2016, v. 25, n. 12, p. -1, doi. 10.1142/S0218126616501498
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- Article
A Low-Power and Area-Efficient 64-Bit Digital Comparator.
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- Journal of Circuits, Systems & Computers, 2016, v. 25, n. 12, p. -1, doi. 10.1142/S0218126616501486
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- Publication type:
- Article
Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic.
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- Journal of Circuits, Systems & Computers, 2016, v. 25, n. 7, p. -1, doi. 10.1142/S0218126616500730
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- Publication type:
- Article
Efficient Audio Filter Using Folded Pipelining Architecture Based on Retiming Using Evolutionary Computation.
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- Journal of Circuits, Systems & Computers, 2015, v. 24, n. 5, p. -1, doi. 10.1142/S0218126615500681
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- Article
SELF-TIMED SECTION-CARRY BASED CARRY LOOKAHEAD ADDERS AND THE CONCEPT OF ALIAS LOGIC.
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- Journal of Circuits, Systems & Computers, 2013, v. 22, n. 4, p. 1, doi. 10.1142/S021812661350028X
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- Article
Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing.
- Published in:
- International Journal of Theoretical Physics, 2018, v. 57, n. 5, p. 1356, doi. 10.1007/s10773-018-3664-z
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- Publication type:
- Article
A Three-Layer Full Adder/Subtractor Structure in Quantum-Dot Cellular Automata.
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- International Journal of Theoretical Physics, 2017, v. 56, n. 9, p. 2848, doi. 10.1007/s10773-017-3453-0
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- Article
On Design of Parity Preserving Reversible Adder Circuits.
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- International Journal of Theoretical Physics, 2016, v. 55, n. 12, p. 5118, doi. 10.1007/s10773-016-3133-5
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- Article
Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic.
- Published in:
- Electronics (2079-9292), 2018, v. 7, n. 10, p. 243, doi. 10.3390/electronics7100243
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- Article
Efficient Fused MAC Unit Using Multi-Operand Parallel Prefix Adder.
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- Radioelectronics & Communications Systems, 2022, v. 65, n. 4, p. 213, doi. 10.3103/S0735272722040057
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- Article
Comparative Analysis of 8-Bit Adder Cells Using CLRCL Full Adder Logic.
- Published in:
- GSTF Journal on Computing, 2014, v. 3, n. 4, p. 104, doi. 10.7603/s40601-013-0046-5
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- Publication type:
- Article