Found: 4
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Jitter Modeling in Digital CDR with Quantization Noise Analysis.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 8, p. 3884, doi. 10.1007/s00034-021-01653-5
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- Article
Jitter and metastability analysis and modeling of multilevel bang‐bang phase detector.
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- International Journal of Circuit Theory & Applications, 2020, v. 48, n. 8, p. 1371, doi. 10.1002/cta.2777
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- Article
Design and Analysis of Wide Tuning Range Ring VCO in 65nm CMOS Technology.
- Published in:
- Radioelectronics & Communications Systems, 2019, v. 62, n. 5, p. 232, doi. 10.3103/S0735272719050054
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- Article
Fault‐tolerant delay cell for ring oscillator application in 65 nm CMOS technology.
- Published in:
- IET Circuits, Devices & Systems (Wiley-Blackwell), 2018, v. 12, n. 3, p. 233, doi. 10.1049/iet-cds.2017.0380
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- Article