Found: 7
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Reversed-Trellis Tail-Biting Convolutional Code (RT-TBCC) Decoder Architecture Design for LTE.
- Published in:
- International Journal of Electrical & Computer Engineering (2088-8708), 2018, v. 8, n. 1, p. 198, doi. 10.11591/ijece.v8i1.pp198-209
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- Article
Rapid Prototyping Methodology of Lightweight Electronic Drivers for Smart Home Appliances.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2016, v. 6, n. 5, p. 2114, doi. 10.11591/ijece.v6i5.11279
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- Article
An Inter-Processor Communication (IPC) Data Sharing Architecture in Heterogeneous MPSoC for OFDMA.
- Published in:
- Journal of ICT Research & Applications, 2018, v. 12, n. 1, p. 70, doi. 10.5614/itbj.ict.res.appl.2018.12.1.5
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- Article
VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm.
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- Journal of ICT Research & Applications, 2016, v. 10, n. 1, p. 57, doi. 10.5614/itbj.ict.res.appl.2016.10.1.5
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- Article
RescueSNN: enabling reliable executions on spiking neural network accelerators under permanent faults.
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- Frontiers in Neuroscience, 2023, v. 17, p. 1, doi. 10.3389/fnins.2023.1159440
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- Article
SNN4Agents: a framework for developing energy-efficient embodied spiking neural networks for autonomous agents.
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- Frontiers in Robotics & AI, 2024, p. 1, doi. 10.3389/frobt.2024.1401677
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- Article
EnforceSNN: Enabling resilient and energy-effcient spiking neural network inference considering approximate DRAMs for embedded systems.
- Published in:
- Frontiers in Neuroscience, 2022, v. 16, p. 1, doi. 10.3389/fnins.2022.937782
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- Article