Found: 8
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Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy.
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- Journal of Circuits, Systems & Computers, 2024, v. 33, n. 5, p. 1, doi. 10.1142/S0218126624500920
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- Article
A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements.
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- Journal of Electronic Testing, 2024, v. 40, n. 1, p. 19, doi. 10.1007/s10836-024-06098-7
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- Article
Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on Memristors.
- Published in:
- Electronics (2079-9292), 2023, v. 12, n. 19, p. 4069, doi. 10.3390/electronics12194069
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- Article
Memristor-Based D-Flip-Flop Design and Application in Built-In Self-Test.
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- Electronics (2079-9292), 2023, v. 12, n. 14, p. 3019, doi. 10.3390/electronics12143019
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- Article
Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications.
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- Journal of Electronic Testing, 2021, v. 37, n. 4, p. 489, doi. 10.1007/s10836-021-05962-0
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- Article
Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier.
- Published in:
- Journal of Circuits, Systems & Computers, 2021, v. 30, n. 5, p. N.PAG, doi. 10.1142/S0218126621200036
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- Article
CC-RTSV: Cross-Cellular Based Redundant TSV Design for 3D ICs.
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- Journal of Circuits, Systems & Computers, 2020, v. 29, n. 11, p. N.PAG, doi. 10.1142/S0218126620501443
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- Article
Chip Stacking Thermal Placement Optimization Algorithm based on Intelligent Computing.
- Published in:
- RISTI: Iberian Journal on Information Systems & Technologies / Revista Ibérica de Sistemas e Tecnologias de Informação, 2016, n. 17A, p. 161, doi. 10.17013/risti.17A.161-167
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- Article