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AES and Related Techniques for Yield Improvement, Metrology and Development Support of ULSI Circuits Manufactured in ≤ 28nm CMOS Technology.
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- Microscopy & Microanalysis, 2014, v. 20, n. S3, p. 2054, doi. 10.1017/S1431927614012008
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Tuning Hyrbrid Ferroelectric and Antiferroelectric Stacks for Low Power FeFET and FeRAM Applications by Using Laminated HSO and HZO films.
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- Advanced Electronic Materials, 2022, v. 8, n. 5, p. 1, doi. 10.1002/aelm.202100837
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- Article
The application of low energy ion scattering spectroscopy (LEIS) in sub 28-nm CMOS technology.
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- Surface & Interface Analysis: SIA, 2017, v. 49, n. 12, p. 1175, doi. 10.1002/sia.6312
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Ferroelectric HfO<sub>2</sub> thin film testing and whole wafer mapping with non-contact corona-Kelvin metrology.
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- Physica Status Solidi. A: Applications & Materials Science, 2017, v. 214, n. 7, p. n/a, doi. 10.1002/pssa.201700249
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Ferroelectric HfO<sub>2</sub> thin film testing and whole wafer mapping with non-contact corona-Kelvin metrology (Phys. Status Solidi A 7∕2017).
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- Physica Status Solidi. A: Applications & Materials Science, 2017, v. 214, n. 7, p. n/a, doi. 10.1002/pssa.201700249
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- Article