Found: 13
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NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors.
- Published in:
- Applied Sciences (2076-3417), 2018, v. 8, n. 3, p. 465, doi. 10.3390/app8030465
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- Article
Para Miner: a generic pattern mining algorithm for multi-core architectures.
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- Data Mining & Knowledge Discovery, 2014, v. 28, n. 3, p. 593, doi. 10.1007/s10618-013-0313-2
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- Article
LWMPI: An MPI library for NoC‐based lightweight manycore processors with on‐chip memory constraints.
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- Concurrency & Computation: Practice & Experience, 2023, v. 35, n. 17, p. 1, doi. 10.1002/cpe.6693
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- Article
Memory allocation anomalies in high‐performance computing applications: A study with numerical simulations.
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- Concurrency & Computation: Practice & Experience, 2021, v. 33, n. 18, p. 1, doi. 10.1002/cpe.6094
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- Article
A comprehensive performance evaluation of the BinLPT workload‐aware loop scheduler.
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- Concurrency & Computation: Practice & Experience, 2019, v. 31, n. 18, p. N.PAG, doi. 10.1002/cpe.5170
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- Article
Energy efficiency and I/O performance of low‐power architectures.
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- Concurrency & Computation: Practice & Experience, 2019, v. 31, n. 18, p. N.PAG, doi. 10.1002/cpe.4948
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- Article
An autonomic‐computing approach on mapping threads to multi‐cores for software transactional memory.
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- Concurrency & Computation: Practice & Experience, 2018, v. 30, n. 18, p. 1, doi. 10.1002/cpe.4506
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- Article
Design methodology for workload-aware loop scheduling strategies based on genetic algorithm and simulation.
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- Concurrency & Computation: Practice & Experience, 2017, v. 29, n. 22, p. n/a, doi. 10.1002/cpe.3933
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- Article
CAP Bench: a benchmark suite for performance and energy evaluation of low-power many-core processors.
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- Concurrency & Computation: Practice & Experience, 2017, v. 29, n. 4, p. n/a, doi. 10.1002/cpe.3892
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- Article
Faithful performance prediction of a dynamic task-based runtime system for heterogeneous multi-core architectures.
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- Concurrency & Computation: Practice & Experience, 2015, v. 27, n. 16, p. 4075, doi. 10.1002/cpe.3555
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- Article
ARTful: A model for user‐defined schedulers targeting multiple high‐performance computing runtime systems.
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- Software: Practice & Experience, 2021, v. 51, n. 7, p. 1622, doi. 10.1002/spe.2977
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- Article
Performance/energy trade‐off in scientific computing: the case of ARM big.LITTLE and Intel Sandy Bridge.
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- IET Computers & Digital Techniques (Wiley-Blackwell), 2015, v. 9, n. 1, p. 27, doi. 10.1049/iet-cdt.2014.0074
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- Article
Automatic Skeleton-Driven Memory Affinity for Transactional Worklist Applications.
- Published in:
- International Journal of Parallel Programming, 2014, v. 42, n. 2, p. 365, doi. 10.1007/s10766-013-0253-x
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- Article