Two‐parallel pipelined fast Fourier transform processors for real‐valued signals.
- Published in:
- IET Circuits, Devices & Systems (Wiley-Blackwell), 2016, v. 10, n. 4, p. 330, doi. 10.1049/iet-cds.2015.0256
- By:
- Publication type:
- Article
Works matching AU Lakshminarayanan, G.
Results: 8
1
2
Reconfigurable 2, 3 and 5-point DFT processing element for SDF FFT architecture using fast cyclic convolution algorithm.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2020, v. 56, n. 12, p. 592, doi. 10.1049/el.2019.4262
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- Publication type:
- Article
3
Reconfigurable 2, 3 and 5‐point DFT processing element for SDF FFT architecture using fast cyclic convolution algorithm.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2020, v. 56, n. 12, p. 592, doi. 10.1049/el.2019.4262
- By:
- Publication type:
- Article
4
Surface-Tension Techniques for Molten Salts.
- Published in:
- Instrumentation Science & Technology, 1969, v. 1, n. 3, p. 261, doi. 10.1080/10739146908543252
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- Publication type:
- Article
5
Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems.
- Published in:
- Circuits, Systems & Signal Processing, 2012, v. 31, n. 3, p. 1049, doi. 10.1007/s00034-011-9367-9
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- Publication type:
- Article
6
Low Power, Area Efficient Architecture for Successive Cancellation Decoder.
- Published in:
- EMITTER International Journal of Engineering Technology, 2022, v. 10, n. 1, p. 170, doi. 10.24003/emitter.v10i1.650
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- Publication type:
- Article
7
Fault Resistant Coplanar QCA Full Adder-Subtractor Using Clock Zone-Based Crossover.
- Published in:
- IETE Journal of Research, 2023, v. 69, n. 1, p. 584, doi. 10.1080/03772063.2020.1838340
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- Publication type:
- Article
8
Design and Implementation of Online Clock Skew Scheme-based Asynchronous Wave-pipelined Distributed Arithmetic Filters on FPGA.
- Published in:
- IETE Journal of Research, 2012, v. 58, n. 6, p. 494, doi. 10.4103/0377-2063.106759
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- Publication type:
- Article