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Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity.
- Published in:
- International Journal of Electronics & Telecommunications, 2021, v. 67, n. 3, p. 385, doi. 10.24425/ijet.2021.137824
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- Article
An Enhanced IEEE1588 Clock Synchronization for Link Delays Based on a System-on-Chip Platform.
- Published in:
- International Journal of Electronics & Telecommunications, 2021, v. 67, n. 2, p. 289, doi. 10.24425/ijet.2021.135978
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- Publication type:
- Article