Adaptive PUF design to authenticate and evaluate heterogeneous IPs in edge computing.
- Published in:
- Journal of Supercomputing, 2024, v. 80, n. 16, p. 24689, doi. 10.1007/s11227-024-06371-8
- By:
- Publication type:
- Article
Works by KANCHANA BHAASKARAN, V. S.
Results: 11
1
2
High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits.
- Published in:
- ETRI Journal, 2019, v. 41, n. 3, p. 383, doi. 10.4218/etrij.2018-0313
- By:
- Publication type:
- Article
3
Power Attack Vulnerability Assessment of Circuit-Level PRESENT Encryption IP Using Artificial Intelligence Mechanisms.
- Published in:
- Journal of Circuits, Systems & Computers, 2024, v. 33, n. 14, p. 1, doi. 10.1142/S0218126624502451
- By:
- Publication type:
- Article
4
Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures.
- Published in:
- Journal of Circuits, Systems & Computers, 2020, v. 29, n. 1, p. N.PAG, doi. 10.1142/S0218126620500164
- By:
- Publication type:
- Article
5
Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL).
- Published in:
- Journal of Circuits, Systems & Computers, 2018, v. 27, n. 4, p. -1, doi. 10.1142/S0218126618500524
- By:
- Publication type:
- Article
6
Design and Implementation of 32-Bit High Valency Jackson Adders.
- Published in:
- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 7, p. -1, doi. 10.1142/S0218126617501237
- By:
- Publication type:
- Article
7
Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique.
- Published in:
- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500797
- By:
- Publication type:
- Article
8
Low Power, High Speed and Area Efficient Binary Count Multiplier.
- Published in:
- Journal of Circuits, Systems & Computers, 2016, v. 25, n. 4, p. 1, doi. 10.1142/S0218126616500274
- By:
- Publication type:
- Article
9
PRE-RESOLVE AND SENSE ADIABATIC LOGIC FOR 100 KHZ TO 500 MHZ FREQUENCY CLASSES.
- Published in:
- Journal of Circuits, Systems & Computers, 2012, v. 21, n. 5, p. -1, doi. 10.1142/S0218126612500454
- By:
- Publication type:
- Article
10
TWO-PHASE SINUSOIDAL POWER-CLOCKED QUASI-ADIABATIC LOGIC CIRCUITS.
- Published in:
- Journal of Circuits, Systems & Computers, 2010, v. 19, n. 2, p. 335, doi. 10.1142/S0218126610006098
- By:
- Publication type:
- Article
11
Lightweight S-Box Architecture for Secure Internet of Things.
- Published in:
- Information (2078-2489), 2018, v. 9, n. 1, p. 13, doi. 10.3390/info9010013
- By:
- Publication type:
- Article