Found: 3
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Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology.
- Published in:
- Journal of Low Power Electronics & Applications, 2014, v. 4, n. 2, p. 77, doi. 10.3390/jlpea4020077
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- Publication type:
- Article
Trading off accuracy and explainability in AI decision-making: findings from 2 citizens' juries.
- Published in:
- 2021
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- Publication type:
- journal article
Comparative study of snake lateral undulation kinematics in model heterogeneous terrain.
- Published in:
- Integrative & Comparative Biology, 2023, v. 63, n. 1, p. 198, doi. 10.1093/icb/icaa125
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- Publication type:
- Article