Works by Hsin, Y.-C.

Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW).

Published in:

Journal of Microelectronic & Electronic Packaging, 2011, v. 8, n. 4, p. 171, doi. 10.4071/imaps.306

By:

• Lau, J. H.;
• Zhan, C.-J.;
• Tzeng, P.-J.;
• Lee, C.-K.;
• Dai, M.-J.;
• Chien, H.-C.;
• Chao, Y.-L.;
• Li, W.;
• Wu, S.-T.;
• Hung, J.-F.;
• Tain, R.-M.;
• Lin, C.-H.;
• Hsin, Y.-C.;
• Chen, C.-C.;
• Chen, S.-C.;
• Wu, C.-Y.;
• Chen, J.-C.;
• Chien, C.-H.;
• Chiang, C.-W.;
• Chang, H.-H.

Publication type:

Article