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A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry.
- Published in:
- Journal of Circuits, Systems & Computers, 2020, v. 29, n. 6, p. N.PAG, doi. 10.1142/S0218126620500954
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- Article
2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations.
- Published in:
- Journal of Circuits, Systems & Computers, 2020, v. 29, n. 6, p. N.PAG, doi. 10.1142/S0218126620500887
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- Publication type:
- Article
High‐voltage on‐chip current sensor design and analysis for battery modules.
- Published in:
- IET Circuits, Devices & Systems (Wiley-Blackwell), 2016, v. 10, n. 6, p. 492, doi. 10.1049/iet-cds.2015.0374
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- Article
A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits.
- Published in:
- Circuits, Systems & Signal Processing, 2018, v. 37, n. 4, p. 1692, doi. 10.1007/s00034-017-0621-7
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- Article