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AES and Related Techniques for Yield Improvement, Metrology and Development Support of ULSI Circuits Manufactured in ≤ 28nm CMOS Technology.
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- Microscopy & Microanalysis, 2014, v. 20, n. S3, p. 2054, doi. 10.1017/S1431927614012008
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METAL CVD: A thermodynamic model.
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- Crystal Research & Technology, 1987, v. 22, n. 3, p. 301, doi. 10.1002/crat.2170220302
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The application of low energy ion scattering spectroscopy (LEIS) in sub 28-nm CMOS technology.
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- Surface & Interface Analysis: SIA, 2017, v. 49, n. 12, p. 1175, doi. 10.1002/sia.6312
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- Article
Characterization of Ultrathin Fully Depleted Silicon‐on‐Insulator Devices Using Subthreshold Slope Method.
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- Physica Status Solidi. A: Applications & Materials Science, 2020, v. 217, n. 24, p. 1, doi. 10.1002/pssa.202000625
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Interface traps in 28 nm node field effect transistors detected by capacitance transient spectroscopy.
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- Physica Status Solidi. A: Applications & Materials Science, 2017, v. 214, n. 7, p. n/a, doi. 10.1002/pssa.201700182
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- Article