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A Bi/Tri-level Self-Adaptive Two-Step DAC Switching Scheme for High-Power Efficiency SAR-Based ADCs.
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- Circuits, Systems & Signal Processing, 2023, v. 42, n. 8, p. 4470, doi. 10.1007/s00034-023-02352-z
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- Article
A 0.6–1.8 V/0.4–1.6 V Input/Output LDO with High PSRR over 50 dB/30 dB in Dual-Modes.
- Published in:
- Circuits, Systems & Signal Processing, 2023, v. 42, n. 1, p. 84, doi. 10.1007/s00034-022-02147-8
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- Publication type:
- Article