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Power bumps and through‐silicon‐vias placement with optimised power mesh structure for power delivery network in three‐dimensional‐integrated circuits.
- Published in:
- IET Computers & Digital Techniques (Wiley-Blackwell), 2013, v. 7, n. 1, p. 11, doi. 10.1049/iet-cdt.2012.0047
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- Article