Works matching DE "GATE array circuits"
Results: 1127
FPGA Accelerated Deep Learning for Industrial and Engineering Applications: Optimal Design Under Resource Constraints.
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- Electronics (2079-9292), 2025, v. 14, n. 4, p. 703, doi. 10.3390/electronics14040703
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- Article
Shallow Learning-Based Intrusion Detection System for In-Vehicle Network: ASIC Implementation.
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- Electronics (2079-9292), 2025, v. 14, n. 4, p. 683, doi. 10.3390/electronics14040683
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Real-time multidimensional detection of longitudinal tears in conveyor belts using FPGA-based parallel acceleration.
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- AI EDAM, 2024, v. 38, p. 1, doi. 10.1017/S0890060424000210
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- Article
Dynamic Analysis and Implementation of FPGA for a New 4D Fractional-Order Memristive Hopfield Neural Network.
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- Fractal & Fractional, 2025, v. 9, n. 2, p. 115, doi. 10.3390/fractalfract9020115
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- Article
Laser system personalizes 0.35-um gate array.
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- Solid State Technology, 1998, v. 41, n. 5, p. 38
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Requirement-driven model-based development methodology applied to the design of a real-time MEG data processing unit.
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- Software & Systems Modeling, 2020, v. 19, n. 6, p. 1567, doi. 10.1007/s10270-020-00797-3
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- Article
Performance analysis of multiple input single layer neural network hardware chip.
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- Multimedia Tools & Applications, 2023, v. 82, n. 18, p. 28213, doi. 10.1007/s11042-023-14627-3
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- Article
Fully FPGA‐based implementation of a modified control strategy for power electronic transformer in railway traction applications.
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- IET Power Electronics (Wiley-Blackwell), 2021, v. 14, n. 11, p. 1904, doi. 10.1049/pel2.12158
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PWM techniques for an asymmetric multilevel binary inverter: an FPGA‐based implementation.
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- IET Power Electronics (Wiley-Blackwell), 2021, v. 14, n. 8, p. 1529, doi. 10.1049/pel2.12131
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- Article
FPGA-based active disturbance rejection velocity control for a parallel DC/DC buck converter-DC motor system.
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- IET Power Electronics (Wiley-Blackwell), 2020, v. 13, n. 2, p. 356, doi. 10.1049/iet-pel.2019.0832
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- Article
Split gate resurf stepped oxide UMOSFET with P-pillar for improved performance.
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- IET Power Electronics (Wiley-Blackwell), 2014, v. 7, n. 4, p. 965, doi. 10.1049/iet-pel.2013.0363
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- Article
Synchronous rectifier driving circuit based on voltage-driven method with energy recovery.
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- IET Power Electronics (Wiley-Blackwell), 2014, v. 7, n. 4, p. 765, doi. 10.1049/iet-pel.2013.0279
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- Article
Hardware nanosecond‐precision timestamping for line‐rate packet capture.
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- IET Networks (Wiley-Blackwell), 2024, v. 13, n. 3, p. 249, doi. 10.1049/ntw2.12114
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- Article
CONTROL DE VELOCIDAD DE UN MOTOR SÍNCRONO DE IMANES PERMANENTES ACCIONADO POR UN INVERSOR TRIFÁSICO MULTINIVEL.
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- Ingenius, Revista Ciencia y Tecnología, 2020, n. 23, p. 97, doi. 10.17163/ings.n23.2020.09
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- Article
Field-programmable gate array (FPGA) hardware design and implementation of a new area efficient elliptic curve crypto-processor.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2021, v. 29, n. 4, p. 2127, doi. 10.3906/elk-2008-8
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- Article
FPGA implementation of LSD-OMP for real-time ECG signal reconstruction.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2021, v. 29, n. 4, p. 1887, doi. 10.3906/elk-2010-108
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- Article
Lightweight signature scheme to protect intellectual properties of Internet of things applications in system on chip field-programmable gate arrays.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2019, v. 27, n. 5, p. 3500, doi. 10.3906/elk-1811-97
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- Article
FPGA-based SOC for hardware implementation of a local histogram-based video shot detector.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2017, v. 25, n. 4, p. 3300, doi. 10.3906/elk-1608-94
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- Article
Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2017, v. 25, n. 3, p. 2044, doi. 10.3906/elk-1506-51
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- Article
Full occlusion handling for pedestrian tracking via hybrid system.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2017, v. 25, n. 2, p. 820, doi. 10.3906/elk-1508-192
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- Article
A 2-D analytical model for cylindrical gate tunnel FET (CG-TFET) based on center potential.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2017, v. 25, n. 2, p. 770, doi. 10.3906/elk-1502-74
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- Article
Total Ionizing Dose Effects of Si Vertical Diffused MOSFET with SiO<sub>2</sub> and Si<sub>3</sub>N<sub>4</sub>/SiO<sub>2</sub> Gate Dielectrics.
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- Active & Passive Electronic Components, 2017, p. 1, doi. 10.1155/2017/9685685
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- Article
Usage and Limitation of Standard Mobility Models for TCAD Simulation of Nanoscaled FD-SOI MOSFETs.
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- Active & Passive Electronic Components, 2015, v. 2015, p. 1, doi. 10.1155/2015/460416
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- Article
Scalable Heteronuclear Architecture of Neutral Atoms Based on EIT.
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- Journal of Experimental & Theoretical Physics, 2023, v. 137, n. 2, p. 202, doi. 10.1134/S1063776123080046
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- Article
Field programmable gate array hardware in the loop validation of fuzzy direct torque control for induction machine drive.
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- Electrical Engineering & Electromechanics, 2023, n. 3, p. 28, doi. 10.20998/2074-272X.2023.3.04
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- Article
FPGA Implementation of Sliding Mode Control and Proportional-Integral-Derivative Controllers for a DC–DC Buck Converter.
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- Technologies (2227-7080), 2024, v. 12, n. 10, p. 184, doi. 10.3390/technologies12100184
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- Article
FPGA-Based Implementation of a New 3-D Multistable Chaotic Jerk System with Two Unstable Balance Points.
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- Technologies (2227-7080), 2023, v. 11, n. 4, p. 92, doi. 10.3390/technologies11040092
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- Article
A TensorFlow Extension Framework for Optimized Generation of Hardware CNN Inference Engines.
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- Technologies (2227-7080), 2020, v. 8, n. 1, p. 6, doi. 10.3390/technologies8010006
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- Article
Designing a Custom CPU Architecture Based on Hardware RTOS and Dynamic Preemptive Scheduler.
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- Mathematics (2227-7390), 2022, v. 10, n. 15, p. 2637, doi. 10.3390/math10152637
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- Article
Computing a Group of Polynomials over a Galois Field in FPGA Architecture.
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- Mathematics (2227-7390), 2021, v. 9, n. 24, p. 3251, doi. 10.3390/math9243251
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- Article
On-the-fly Computation Method in Field-Programmable Gate Array for Analog-to-Digital Converter Linearity Testing.
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- Journal of Engineering & Technological Sciences, 2018, v. 50, n. 5, p. 589, doi. 10.5614/j.eng.technol.sci.2018.50.5.1
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- Article
SELF-TIMED LOOK UP TABLE FOR ULAs AND FPGAs.
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- Radio Electronics, Computer Science, Control, 2021, n. 1, p. 36, doi. 10.15588/1607-3274-2021-1-4
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- Article
A brain machine interface framework for exploring proactive control of smart environments.
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- Scientific Reports, 2024, v. 14, n. 1, p. 1, doi. 10.1038/s41598-024-60280-7
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- Article
A brain machine interface framework for exploring proactive control of smart environments.
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- Scientific Reports, 2024, v. 14, n. 1, p. 1, doi. 10.1038/s41598-024-60280-7
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- Article
Numerical Simulation and Mathematical Modeling of 3D DG SOI MOSFET with the Influence of Biasing with Back Gate.
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- Journal of Nano- & Electronic Physics, 2017, v. 9, n. 5, p. 1, doi. 10.21272/jnep.9(5).05002
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- Article
Two Dimensional Modeling of III-V Heterojunction Gate All Around Tunnel Field Effect Transistor.
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- Journal of Nano- & Electronic Physics, 2017, v. 9, n. 1, p. 01030-1, doi. 10.21272/jnep.9(1).01030
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- Article
Design Device for Subthreshold Slope in DG Fully Depleted SOI MOSFET.
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- Journal of Nano- & Electronic Physics, 2017, v. 9, n. 1, p. 01022-1, doi. 10.21272/jnep.9(1).01022
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- Article
A Two Dimensional Surface Potential Model for Triple Material Double Gate Junctionless Field Effect Transistor.
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- Journal of Nano- & Electronic Physics, 2016, v. 8, n. 4, p. 1, doi. 10.21272/jnep.8(4(1)).04042
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- Article
Effects of High-k Dielectrics with Metal Gate for Electrical Characteristics of SOI TRI-GATE FinFET Transistor.
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- Journal of Nano- & Electronic Physics, 2016, v. 8, n. 4, p. 1, doi. 10.21272/jnep.8(4(1)).04037
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- Article
Effect of High-k Oxide on Double Gate Transistor Embedded in RF Colpitts Oscillator.
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- Journal of Nano- & Electronic Physics, 2016, v. 8, n. 4, p. 1, doi. 10.21272/jnep.8(4(1)).04022
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- Article
Digital circuits test optimization by multifunctional components.
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- Information Sciences & Technologies: Bulletin of the ACM Slovakia, 2012, v. 4, n. 3, p. 54
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- Article
A Device-on-Chip Solution for Real-Time Diffuse Correlation Spectroscopy Using FPGA.
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- Biosensors (2079-6374), 2024, v. 14, n. 8, p. 384, doi. 10.3390/bios14080384
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- Article
Bichromatic tuning of reflection bands in integrated CLC reflectors for optical switches, gates, and logic.
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- Applied Physics B: Lasers & Optics, 2015, v. 118, n. 3, p. 379, doi. 10.1007/s00340-014-5995-7
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- Article
PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA.
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- Future Internet, 2024, v. 16, n. 9, p. 307, doi. 10.3390/fi16090307
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- Article
Non-Profiled Unsupervised Horizontal Iterative Attack against Hardware Elliptic Curve Scalar Multiplication Using Machine Learning.
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- Future Internet, 2024, v. 16, n. 2, p. 45, doi. 10.3390/fi16020045
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- Article
Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA.
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- Future Internet, 2023, v. 15, n. 5, p. 186, doi. 10.3390/fi15050186
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- Article
Configurable Hardware Core for IoT Object Detection.
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- Future Internet, 2021, v. 13, n. 11, p. 280, doi. 10.3390/fi13110280
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- Article
An SSD-MobileNet Acceleration Strategy for FPGAs Based on Network Compression and Subgraph Fusion.
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- Forests (19994907), 2023, v. 14, n. 1, p. 53, doi. 10.3390/f14010053
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- Article
FPGA Hardware Realization of Membrane Calculation Optimization Algorithm with Great Parallelism.
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- Symmetry (20738994), 2022, v. 14, n. 10, p. N.PAG, doi. 10.3390/sym14102199
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- Article
High Performance Parallel Pseudorandom Number Generator on Cellular Automata.
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- Symmetry (20738994), 2022, v. 14, n. 9, p. 1869, doi. 10.3390/sym14091869
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- Article