A Supramolecular Counter Circuit Based on Cyanine Dye Assembly.
- Published in:
- Chemistry - A European Journal, 2020, v. 26, n. 58, p. 13235, doi. 10.1002/chem.202001240
- By:
- Publication type:
- Article
Works matching DE "SEQUENTIAL circuits"
Results: 143
1
2
Powering DNA strand-displacement reactions with a continuous flow reactor.
- Published in:
- Natural Computing, 2021, v. 20, n. 4, p. 821, doi. 10.1007/s11047-020-09795-2
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- Publication type:
- Article
3
From high-level modeling toward efficient and trustworthy circuits.
- Published in:
- International Journal on Software Tools for Technology Transfer, 2019, v. 21, n. 2, p. 143, doi. 10.1007/s10009-017-0462-5
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- Publication type:
- Article
4
Boolean and Sequential Logic in a One‐Memristor‐One‐Resistor (1M1R) Structure for In‐Memory Computing.
- Published in:
- Advanced Electronic Materials, 2018, v. 4, n. 9, p. 1, doi. 10.1002/aelm.201800229
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- Publication type:
- Article
5
Parts-per-Billion Detection of Hydrogen Sulfide via Cavity Ring-Down Spectroscopy.
- Published in:
- Photonics, 2025, v. 12, n. 3, p. 284, doi. 10.3390/photonics12030284
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- Publication type:
- Article
6
Automated Sequential Control for Domestic Distribution Circuit Board.
- Published in:
- International Review of Automatic Control, 2012, v. 5, n. 1, p. 72
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- Publication type:
- Article
7
A Parallel Test Application Method towards Power Reduction.
- Published in:
- Journal of Electronic Testing, 2017, v. 33, n. 2, p. 157, doi. 10.1007/s10836-017-5656-y
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- Publication type:
- Article
8
Editorial.
- Published in:
- 2015
- By:
- Publication type:
- Editorial
9
One More Class of Sequential Circuits having Combinational Test Generation Complexity.
- Published in:
- Journal of Electronic Testing, 2015, v. 31, n. 3, p. 321, doi. 10.1007/s10836-015-5527-3
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- Publication type:
- Article
10
A Probabilistic Approach to Diagnose SETs in Sequential Circuits.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 3, p. 317, doi. 10.1007/s10836-013-5361-4
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- Publication type:
- Article
11
A New Design-for-Testability Method Based on Thru-Testability.
- Published in:
- Journal of Electronic Testing, 2011, v. 27, n. 5, p. 583, doi. 10.1007/s10836-011-5241-8
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- Publication type:
- Article
12
Performance Optimization of Transmission Gate-Based D Flip-Flop using Clock Gating Technique.
- Published in:
- International Journal of Wireless & Ad Hoc Communication, 2025, v. 9, n. 1, p. 18, doi. 10.54216/IJWAC.090102
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- Publication type:
- Article
13
A Circularly Polarized Miniaturized Patch Array Using Combination of Circle and Rectangular Lines in the Sequential Phase Feed Structure.
- Published in:
- Applied Computational Electromagnetics Society Journal, 2017, v. 32, n. 4, p. 339
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- Publication type:
- Article
14
Integrated non-volatile plasmonic switches based on phase-change-materials and their application to plasmonic logic circuits.
- Published in:
- Scientific Reports, 2021, v. 11, n. 1, p. 1, doi. 10.1038/s41598-021-98418-6
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- Publication type:
- Article
15
Design of new reversible quaternary flip-flops.
- Published in:
- International Journal of Quantum Information, 2017, v. 15, n. 4, p. -1, doi. 10.1142/S0219749917500241
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- Publication type:
- Article
16
AN OVERVIEW OF THE SOLUTIONS FOR THE IMPLEMENTATION OF ASYNCHRONOUS DIGITAL SYSTEMS.
- Published in:
- Annals of the University Dunarea de Jos of Galati Fascicle III: Electrotechnics, Electronics, Automatic Control & Informatics, 2016, v. 39, n. 1, p. 23
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- Publication type:
- Article
17
A Universal BIST Approach for Virtex-Ultrascale Architecture.
- Published in:
- Computer Systems Science & Engineering, 2023, v. 45, n. 3, p. 2705, doi. 10.32604/csse.2023.025941
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- Publication type:
- Article
18
A novel reversible design for double edge triggered flip-flops and new designs of reversible sequential circuits.
- Published in:
- Computer Systems Science & Engineering, 2014, v. 29, n. 3, p. 197
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- Publication type:
- Article
19
Approximate Evaluation of the Efficiency of Synchronous and Self-Timed Methodologies in Problems of Designing Failure-Tolerant Computing and Control Systems.
- Published in:
- Automation & Remote Control, 2022, v. 83, n. 2, p. 264, doi. 10.1134/S0005117922020084
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- Publication type:
- Article
20
Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits.
- Published in:
- Automation & Remote Control, 2021, v. 82, n. 11, p. 1949, doi. 10.1134/S0005117921110102
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- Publication type:
- Article
21
HYBRID MODULATION SCHEME FOR CASCADED H-BRIDGE INVERTER CELLS.
- Published in:
- Nigerian Journal of Technology, 2015, v. 34, n. 1, p. 193, doi. 10.4314/nit.v34i1.24
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- Publication type:
- Article
22
Analytical Computation of the Area of Pinched Hysteresis Loops of Ideal Mem-Elements.
- Published in:
- Radioengineering, 2013, v. 22, n. 1, p. 132
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- Publication type:
- Article
23
A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test.
- Published in:
- Radioengineering, 2011, v. 20, n. 2, p. 533
- By:
- Publication type:
- Article
24
Reversible Flip-Flops in Quantum-Dot Cellular Automata.
- Published in:
- International Journal of Theoretical Physics, 2017, v. 56, n. 9, p. 2990, doi. 10.1007/s10773-017-3466-8
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- Publication type:
- Article
25
Analysis of 6(4) - Valued Memory.
- Published in:
- Electronics & Electrical Engineering, 2014, v. 20, n. 6, p. 89, doi. 10.5755/j01.eee.20.6.7274
- By:
- Publication type:
- Article
26
An Investigation of Possibilities of Improving Random Test Generation for Non-scan Sequential Circuits.
- Published in:
- Electronics & Electrical Engineering, 2011, n. 114, p. 11
- By:
- Publication type:
- Article
27
Verification of Initialization Sequences for Sequential Circuits.
- Published in:
- Electronics & Electrical Engineering, 2011, n. 112, p. 61
- By:
- Publication type:
- Article
28
On Delay Test Generation for Non-scan Sequential Circuits at Functional Level.
- Published in:
- Electronics & Electrical Engineering, 2011, n. 109, p. 67
- By:
- Publication type:
- Article
29
HYBRID MODEL FOR SEQUENTIAL AND COMBINATIONAL CIRCUITS MODELLEDON NEW XOR-XNOR GATES FOR LOW POWER APPLICATIONS.
- Published in:
- Ilkogretim Online, 2021, v. 20, n. 5, p. 4115, doi. 10.17051/ilkonline.2021.05.451
- By:
- Publication type:
- Article
30
Dynamic current mode logic based flip-flop design for robust and low-power security integrated circuits.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2017, v. 53, n. 18, p. 1236, doi. 10.1049/el.2017.2415
- By:
- Publication type:
- Article
31
Ultra low overhead error mask flip-flop in near threshold voltage processor design.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2016, v. 52, n. 21, p. 1799, doi. 10.1049/el.2016.0091
- By:
- Publication type:
- Article
32
Parasitic Coupling in 3D Sequential Integration: The Example of a Two-Layer 3D Pixel †.
- Published in:
- Technologies (2227-7080), 2022, v. 10, n. 2, p. N.PAG, doi. 10.3390/technologies10020038
- By:
- Publication type:
- Article
33
Graph of Outputs in the Process of Synthesis Directed at CPLDs.
- Published in:
- Mathematics (2227-7390), 2019, v. 7, n. 12, p. 1171, doi. 10.3390/math7121171
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- Publication type:
- Article
34
基于Multisim仿真数字逻辑实验教学改革.
- Published in:
- Research & Exploration in Laboratory, 2019, v. 38, n. 9, p. 228
- By:
- Publication type:
- Article
35
Reform in Digital Electronics Teaching Based on PSoC.
- Published in:
- Research & Exploration in Laboratory, 2014, v. 33, n. 8, p. 163
- By:
- Publication type:
- Article
36
Exploration and Exploitation During Sequential Search.
- Published in:
- Cognitive Science, 2009, v. 33, n. 3, p. 530, doi. 10.1111/j.1551-6709.2009.01021.x
- By:
- Publication type:
- Article
37
MODELO SEMÂNTICO DE OPERAÇÕES ARITMÉTICAS E LÓGICAS PARA HARDWARE VIRTUAL.
- Published in:
- Colloquium Exactarum, 2024, v. 16, n. 1, p. 1, doi. 10.5747/ce.2024.v16.e417
- By:
- Publication type:
- Article
38
ENHANCED CLOCK GATING TECHNIQUE FOR POWER OPTIMIZATION IN SRAM AND SEQUENTIAL CIRCUIT.
- Published in:
- Journal of Automation, Mobile Robotics & Intelligent Systems, 2021, v. 15, n. 2, p. 32, doi. 10.14313/JAMRIS/2-2021/11
- By:
- Publication type:
- Article
39
ASIC and FPGA Implementation of an Adaptive Convolutional Encoder and Viterbi Decoder.
- Published in:
- IETE Journal of Research, 2025, v. 71, n. 3, p. 768, doi. 10.1080/03772063.2024.2442035
- By:
- Publication type:
- Article
40
Design of Reversible Serial Adder Based on EPOE Expressions for Computational Applications.
- Published in:
- IETE Journal of Research, 2024, v. 70, n. 9, p. 7396, doi. 10.1080/03772063.2024.2353349
- By:
- Publication type:
- Article
41
Multiple-Controlled Toffoli and Multiple-Controlled Fredkin Reversible Logic Gates-Based Reversible Synchronous Counter Design.
- Published in:
- IETE Journal of Research, 2024, v. 70, n. 5, p. 5176, doi. 10.1080/03772063.2023.2228747
- By:
- Publication type:
- Article
42
Design of CNTFET-based Ternary Ring and Up–Down Counter Cells.
- Published in:
- IETE Journal of Research, 2024, v. 70, n. 5, p. 5149, doi. 10.1080/03772063.2023.2225469
- By:
- Publication type:
- Article
43
A Novel Double-Gate MOSFET Architecture as an Inverter.
- Published in:
- IETE Journal of Research, 2023, v. 69, n. 11, p. 8218, doi. 10.1080/03772063.2022.2048712
- By:
- Publication type:
- Article
44
Circuit Level Implementation for Insulated Shallow Extension Silicon on Nothing (ISE-SON) MOSFET: A Novel Device Architecture.
- Published in:
- IETE Journal of Research, 2013, v. 59, n. 4, p. 404, doi. 10.4103/0377-2063.118053
- By:
- Publication type:
- Article
45
System-on-chips Design Using ISCAS Benchmark Circuits - An Approach to Fault Injection and Simulation Based on Verilog HDL.
- Published in:
- IETE Journal of Research, 2012, v. 58, n. 2, p. 107, doi. 10.4103/0377-2063.96177
- By:
- Publication type:
- Article
46
Power-delay Trade-offs in CMOS Circuits Using Self-bias Transistors.
- Published in:
- IETE Journal of Research, 2012, v. 58, n. 1, p. 24, doi. 10.4103/0377-2063.94078
- By:
- Publication type:
- Article
47
A Novel Simulation Approach for Fault Injection Mechanism Assessing Dependability of Cybersecurity Attacks.
- Published in:
- Journal of Circuits, Systems & Computers, 2024, v. 33, n. 6, p. 1, doi. 10.1142/S021812662450097X
- By:
- Publication type:
- Article
48
A Novel Test Pattern Optimization Method Using Recurrent Neural Network.
- Published in:
- Journal of Circuits, Systems & Computers, 2024, v. 33, n. 4, p. 1, doi. 10.1142/S0218126624500762
- By:
- Publication type:
- Article
49
QCA-Based Pulse/Bit Sequence Detector Using Low Quantum Cost D-Flip Flop.
- Published in:
- Journal of Circuits, Systems & Computers, 2023, v. 32, n. 5, p. 1, doi. 10.1142/S0218126623500822
- By:
- Publication type:
- Article
50
Exploiting Energy–Quality (E–Q) Tradeoffs: A Case Study on Color-to-Grayscale Converters with Approximate Design on FPGA.
- Published in:
- Journal of Circuits, Systems & Computers, 2021, v. 30, n. 04, p. N.PAG, doi. 10.1142/S0218126621500626
- By:
- Publication type:
- Article