Works matching VHDL (Computer hardware description language)

Results: 122

A Review on FPGA Implementation of Distributed Canny Edge Detector.

Published in:

Grenze International Journal of Engineering & Technology (GIJET), 2017, v. 3, n. 3, p. 94

By:

Chandrashekar, N. S.;
Nataraj, K. R.

Publication type:

Article

A Cryptosystem Architecture and Design for Encrypted Data Transmissions.

Published in:

Electrotehnica, Electronica, Automatica, 2019, v. 67, n. 2, p. 76

By:

BABA-AHMED, Mohammed Zakarya;
BENMANSOUR, Fatima Zohra;
SEDJELMACI, Amina

Publication type:

Article

Microprocessor design using hardware description language.

Published in:

European Journal of Engineering Education, 2008, v. 33, n. 4, p. 425, doi. 10.1080/03043790802253384

By:

Mita, Rosario;
Palumbo, Gaetano

Publication type:

Article

Improvements in space radiation-tolerant FPGA implementation of land surface temperature-split window algorithm.

Published in:

International Journal of Electrical & Computer Engineering (2088-8708), 2021, v. 11, n. 5, p. 3844, doi. 10.11591/ijece.v11i5.pp3844-3854

By:

El Makhloufi, Assaad;
Chekroun, Nisrine;
Tagmouti, Noha;
El Adib, Samir;
Raissouni, Naoufal

Publication type:

Article

VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes.

Published in:

International Journal of Electrical & Computer Engineering (2088-8708), 2017, v. 7, n. 4, p. 1824, doi. 10.11591/ijece.v7i4.pp1824-1832

By:

Boudaoud, A.;
El Haroussi, M.;
Abdelmounim, E.

Publication type:

Article

FPGA Based Control Method for Three Phase BLDC Motor.

Published in:

International Journal of Electrical & Computer Engineering (2088-8708), 2016, v. 6, n. 4, p. 1434, doi. 10.11591/ijece.v6i4.10103

By:

Suneeta;
Srinivasan, R.;
Sagar, Ram

Publication type:

Article

Evaluation of High Speed Hardware Multipliers - Fixed Point and Floating point.

Published in:

International Journal of Electrical & Computer Engineering (2088-8708), 2013, v. 3, n. 6, p. 805, doi. 10.11591/ijece.v3i6.4185

By:

Ahmed, Awais;
Abbas, Syed Haider;
Siddique, Muhammad Faheem;
Haider, Hussnain

Publication type:

Article

A Unified Codec Scheme for reduction of Area and Crosstalk in RC and RLC Modeled Interconnects using both Bus Encoding and Shielding Insertion Technique.

Published in:

International Journal of Electrical & Computer Engineering (2088-8708), 2013, v. 3, n. 4, p. 524, doi. 10.11591/ijece.v3i4.3173

By:

Duggal, Dhriti;
Singh, Gurmohan;
Kaur, Manjit

Publication type:

Article

Simulating the effects of logic faults in implementation-level VITAL-compliant models.

Published in:

Computing, 2019, v. 101, n. 2, p. 77, doi. 10.1007/s00607-018-0651-4

By:

Tuzov, Ilya;
de Andrés, David;
Ruiz, Juan-Carlos

Publication type:

Article

Synthesis and implementation of the ordered access memory in programmable logic devices.

Published in:

Metallurgical & Mining Industry, 2016, n. 4, p. 58

By:

Lishchyna, Nataliia;
Lishchyna, Valerii;
Herasymchuk, Oleh;
Yashchuk, Andrii

Publication type:

Article

Image Encryption using Simple Algorithm on FPGA.

Published in:

Telkomnika, 2015, v. 13, n. 4, p. 1153, doi. 10.12928/TELKOMNIKA.v13i4.1787

By:

Prasetio, Barlian Henryranu;
Setiawan, Eko;
Muttaqin, Adharul

Publication type:

Article

FPGA Implementation ofLow-Area Square Root Calculator.

Published in:

Telkomnika, 2015, v. 13, n. 4, p. 1145, doi. 10.12928/TELKOMNIKA.v13i4.1894

By:

Jidin, Aiman Zakwan;
Sutikno, Tole

Publication type:

Article

Analysis and Performance Evaluation of PD-like Fuzzy Logic Controller Design Based on Matlab and FPGA.

Published in:

IAENG International Journal of Computer Science, 2010, v. 37, n. 2, p. 146

By:

Obaid, Zeyad Assi;
Sulaiman, Nasri;
Marhaban, M. H.;
Hamidon, M. N.

Publication type:

Article

Hardware Architecture for the Implementation of the Discrete Wavelet Transform in two Dimensions.

Published in:

Ingeniería y Competitividad, 2014, v. 16, n. 1, p. 69

By:

Ríos-Cotazo, Norma X.;
Bernal-Noreña, Álvaro

Publication type:

Article

Synthesizable High Level Hardware Descriptions.

Published in:

New Generation Computing, 2010, v. 28, n. 4, p. 339, doi. 10.1007/s00354-008-0093-1

By:

Gillenwater, Jennifer;
Malecha, Gregory;
Salama, Cherif;
Zhu, Angela;
Taha, Walid;
Grundy, Jim;
O'leary, John

Publication type:

Article

Development of Library Components for Floating Point Processor.

Published in:

Journal of Ultra Scientist of Physical Sciences - Section A (Mathematics), 2021, v. 33, n. 4, p. 42, doi. 10.22147/jusps-A/330402

By:

SHARMA, SUBHASH KUMAR;
DUBEY, SHRI PRAKASH;
MISHRA, ANIL KUMAR

Publication type:

Article

Contribution to Synchronization and Tracking Modelisation in a CDMA Receiver.

Published in:

Journal of Engineering (2314-4912), 2013, p. 1, doi. 10.1155/2013/936495

By:

Hassani, Aicha Alami;
Zouak, Mohcine;
Mrabti, Mostafa

Publication type:

Article

Digital control technologies for improving the power quality of power supplies.

Published in:

Neural Computing & Applications, 2013, v. 22, p. 235, doi. 10.1007/s00521-012-1058-3

By:

Shah, P.;
Saxena, Rakesh;
Chawla, M.

Publication type:

Article

Neural network training based on FPGA with floating point number format and it's performance.

Published in:

Neural Computing & Applications, 2011, v. 20, n. 2, p. 195, doi. 10.1007/s00521-010-0423-3

By:

Çavuşlu, Mehmet;
Karakuzu, Cihan;
Şahin, Suhap;
Yakut, Mehmet

Publication type:

Article

Suspended gate field effect transistor type microelectromechanical systems resonators modelling with micro-Raman spectroscopy measured residual stress.

Published in:

Micro & Nano Letters (Wiley-Blackwell), 2013, v. 8, n. 10, p. 614, doi. 10.1049/mnl.2013.0272

By:

Chenxu Zhao;
Mengwei Li;
Xin Guo;
Zewen Liu

Publication type:

Article

Design of 4 bits Combinational Lock Using VHDL.

Published in:

International Journal of Electrical, Electronics & Computer Systems, 2014, v. 19, n. 2, p. 15

By:

Ogeh, Jenny Ebitonere

Publication type:

Article

Relating Event and Trace Semantics of Hardware Description Languages.

Published in:

Computer Journal, 2002, v. 45, n. 1, p. 27, doi. 10.1093/comjnl/45.1.27

By:

Gordon, Michael J. C.

Publication type:

Article

Overview on Strategies and Approaches for FPGA Programming.

Published in:

Telkomnika, 2014, v. 12, n. 2, p. 273, doi. 10.12928/TELKOMNIKA.v12i2.1948

By:

Tole Sutikno;
Nik Idris, Nik Rumzi;
Jidin, Aiman Zakwan

Publication type:

Article

DESIGN AND IMPLEMENTATION OF GA-BASED FUZZY SYSTEM ON FPGA CHIP.

Published in:

Cybernetics & Systems, 2008, v. 39, n. 1, p. 79, doi. 10.1080/01969720701710220

By:

Ching-Chang Wong;
Yu-Han Lin

Publication type:

Article

Development of IEEE-754 to Decimal Conversion of Library Components for Floating Point Arithmetic Logic Unit.

Published in:

International Transactions in Mathematical Sciences & Computer, 2011, v. 4, n. 2, p. 165

By:

Jha, Udai Kumar;
Sharma, Subhash Kumar

Publication type:

Article

FPGA Implementation of a Hybrid On-line Process Monitoring in PC Based Real-Time Systems.

Published in:

Serbian Journal of Electrical Engineering, 2011, v. 8, n. 1, p. 37, doi. 10.2298/SJEE1101037J

By:

Jovanović, Bojan;
Jevtić, Milun

Publication type:

Article

Cardiac Arrhythmias Detection by Neural Networks: VHDL Modeling and Synthesis on FPGA.

Published in:

International Review of Automatic Control, 2012, v. 5, n. 5, p. 689

By:

Chalabi, Z.;
Chalabi, D.;
Amara, A.;
Berrached, N.

Publication type:

Article

Improved Design of Bit Synchronization Clock Extraction in Digital Communication System.

Published in:

Journal of Electrical & Computer Engineering, 2018, p. 1, doi. 10.1155/2018/8024168

By:

Duan, Huimin;
Huang, Hui;
Li, Cuihua

Publication type:

Article

Efficient Hardware Implementations for Tripling Oriented Elliptic Curve Crypto-System.

Published in:

International Review on Computers & Software, 2014, v. 9, n. 4, p. 609

By:

Alkhatib, Mohammad;
Salem, Adel Al

Publication type:

Article

FPGA-Based Farsi Handwritten Digit Recognition System.

Published in:

International Journal of Simulation: Systems, Science & Technology, 2010, v. 11, n. 2, p. 17

By:

Moradi, Marzieh;
Pourmina, Mohammad Ali;
Razzazi, Farbod

Publication type:

Article

Hardware implementation of evolutionary algorithms using dynamic reconfiguration technology.

Published in:

Natural Computing, 2015, v. 14, n. 4, p. 593, doi. 10.1007/s11047-014-9476-z

By:

Kanasugi, Akinori;
Tsukahara, Akihiko;
Ando, Ki

Publication type:

Article

A novel design of variable-rate RS encoder for ubiquitous high performance multimedia service in Gbps transmission system.

Published in:

Journal of Supercomputing, 2011, v. 55, n. 2, p. 192, doi. 10.1007/s11227-010-0441-z

By:

Yang Sun Lee;
Sang-Soo Yeo

Publication type:

Article

DESIGN AND SIMULATION OF SINGLE-PRECISION INEXACT FLOATING-POINT ADDER/SUBTRACTOR.

Published in:

i-Manager's Journal on Electronics Engineering, 2016, v. 6, n. 4, p. 7, doi. 10.26634/jele.6.4.8087

By:

KUMAR, B. VENKATA VINOD;
BASHA, S. K. MAHABOOB

Publication type:

Article

DESIGN AND ANALYSIS OF 32X32 BIT ALU USING HIGH-SPEED VEDIC-WALLACE MULTIPLIER BASED ON VEDIC MATHEMATICS.

Published in:

i-Manager's Journal on Electronics Engineering, 2016, v. 6, n. 3, p. 7, doi. 10.26634/jele.6.3.5954

By:

KONDU DHARITHA REDDY;
MAHESH, P. V.

Publication type:

Article

AN EFFICIENT ARCHITECTURE FOR SINGLE PRECISION FLOATING POINT MULTIPLIER USING VARIOUS ALGORITHMS.

Published in:

i-Manager's Journal on Electronics Engineering, 2015, v. 5, n. 3, p. 11, doi. 10.26634/jele.5.3.3393

By:

KUMAR K., CHARAN;
KUMAR K., SUNIL

Publication type:

Article

Parallelized and pipelined hardware implementation of computationally expensive prediction filters.

Published in:

Concurrency & Computation: Practice & Experience, 2009, v. 21, n. 18, p. 2478, doi. 10.1002/cpe.1480

By:

Gracia, Luis;
Perez-Vidal, Carlos

Publication type:

Article

A Reconfigurable Hybrid Architecture for HomePNA3.1/Ethernet MAC.

Published in:

Majlesi Journal of Electrical Engineering, 2011, v. 5, n. 4, p. 46

By:

Dermany, Mohammad Khalily;
Payegozar, Hamid;
Beheshti, Seyed Ahmad;
Ahmadi, Mohammad

Publication type:

Article

VHDL DESIGN FOR A SPEED LIMIT SIGN SEGMENTATION ALGORITHM.

Published in:

IADIS International Journal on Computer Science & Information Systems, 2017, v. 12, n. 2, p. 32

By:

Rouabeh, Hanene;
Abdelmoula, Chokri;
Masmoudi, Mohamed

Publication type:

Article

Performance Evaluation of Squaring Operation by Vedic Mathematics.

Published in:

IETE Journal of Research, 2011, v. 57, n. 1, p. 39, doi. 10.4103/0377-2063.78327

By:

Kasliwal, Prabha S.;
Patil, B. P.;
Gautam, D. K.

Publication type:

Article

NSL: A Neuro–Symbolic Language for a Neuro–Symbolic Processor (NSP).

Published in:

International Journal of Neural Systems, 2003, v. 13, n. 2, p. 93, doi. 10.1142/S0129065703001480

By:

Burattini, Ernesto;
de Francesco, Antonio;
de Gregorio, Massimo

Publication type:

Article

Implementation of a Pulse Coupled Neural Network in FPGA.

Published in:

International Journal of Neural Systems, 2000, v. 10, n. 3, p. 171, doi. 10.1142/S0129065700000156

By:

Waldemark, Joakim;
Millberg, Mikael;
Lindblad, Thomas;
Waldemark, Karina;
Becanovic, Vlatko

Publication type:

Article

Implementation of NonLinear Controller with Anti-Windup on Xilinx FPGA.

Published in:

Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ), 2024, v. 49, n. 9, p. 13005, doi. 10.1007/s13369-024-08912-y

By:

Ahmed, Samet;
Yahia, Kourd;
Dimitri, Lefebvre

Publication type:

Article

Verifying Digital Components of Physical Systems: Experimental Evaluation of Test Quality.

Published in:

Russian Physics Journal, 2018, v. 60, n. 11, p. 2012, doi. 10.1007/s11182-018-1317-6

By:

Laputenko, A. V.;
López, J. E.;
Yevtushenko, N. V.

Publication type:

Article

Software tool for efficient FPGA design of direct data domain approach for space-time adaptive processing.

Published in:

Electronics Letters (Wiley-Blackwell), 2013, v. 49, n. 13, p. 1, doi. 10.1049/el.2013.1307

By:

Jarrah, A.;
Jamali, M.

Publication type:

Article

Invariant-Based Safety Assessment of FPGA Projects: Conception and Technique.

Published in:

Computers (2073-431X), 2021, v. 10, n. 10, p. 125, doi. 10.3390/computers10100125

By:

Kharchenko, Vyacheslav;
Illiashenko, Oleg;
Sklyar, Vladimir

Publication type:

Article

CONSTRUÇÃO DE UM BRAÇO ROBÓTICO CONTROLADO A PARTIR DE UM FPGA.

Published in:

Colloquium Exactarum, 2012, v. 4, n. 1, p. 1, doi. 10.5747/ce.2012.v04.n1.e040

By:

Mimoso Souza, Geovane;
Torres Delgado, Martha Ximena;
Xavier Cruz, Tiago

Publication type:

Article

MODIFIKUOTO POŽYMIŲ VAIZDE IŠSKYRIMO SURF ALGORITMO OBJEKTUI SEKTI REALIUOJU LAIKU ĮGYVENDINIMAS LAUKU PROGRAMUOJAMOJE LOGINĖJE MATRICOJE.

Published in:

Science: Future of Lithuania / Mokslas: Lietuvos Ateitis, 2013, v. 5, n. 2, p. 74, doi. 10.3846/mla.2013.12

By:

Sledevič, Tomyslav

Publication type:

Article

High Performance Fuzzy Systems for Real World Problems.

Published in:

Advances in Fuzzy Systems, 2012, p. 1, doi. 10.1155/2012/316187

By:

Ross, OscarMontiel;
Cruz, Roberto Sepúlveda;
Castillo, Oscar;
Basturk, Alper

Publication type:

Article

Algorithm & Design of an Efficient Floating Point ADD/SUB Unit for an Experimental CPU.

Published in:

International Journal of Intelligent Information Technology Application, 2009, v. 2, n. 6, p. 273

By:

Joshi, A.;
Lam, S. L.;
Chan, Y. Y.

Publication type:

Article

VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators.

Published in:

PLoS ONE, 2016, v. 11, n. 12, p. 1, doi. 10.1371/journal.pone.0168300

By:

Tlelo-Cuautle, Esteban;
Quintas-Valles, Antonio de Jesus;
de la Fraga, Luis Gerardo;
Rangel-Magdaleno, Jose de Jesus

Publication type:

Article