Works matching Cache memory
Results: 1391
Minimizing the Cache Memory Miss Ratio Using Modified Replacement Algorithm (MCAR).
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- Ingénierie des Systèmes d'Information, 2024, v. 29, n. 2, p. 697, doi. 10.18280/isi.290231
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Some preliminary results of memory cache analysis with the use of non-extensive.
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- Annales UMCS, Informatica, 2016, v. 16, n. 2, p. 43, doi. 10.17951/AI.2016.16.2.43
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A Performance Comparison of Java Cache Memory Implementations.
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- Gümüshane Üniversitesi Fen Bilimleri Enstitüsü Dergisi, 2020, v. 10, n. 3, p. 844, doi. 10.17714/gumusfenbil.637942
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دراسة العوامل المؤثرة بنسبة الإصابة في الذاكرة المخبئية ضمن نظام متعدد المعالجات
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- Tikrit Journal of Engineering Sciences, 2016, v. 23, n. 4, p. 23
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Aspects of Cache Memory Simulation using Programs under Windows and UNIX Operating Systems.
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- Journal of Computer Science & Control Systems, 2011, v. 4, n. 2, p. 55
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A Comparative Study of Simulation Program for Cache Memory Performance Assessment.
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- Journal of Computer Science & Control Systems, 2009, v. 2, n. 2, p. 39
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Memory and Cache Contention Denial-of-Service Attack in Mobile Edge Devices.
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- Applied Sciences (2076-3417), 2021, v. 11, n. 5, p. 2385, doi. 10.3390/app11052385
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A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based Cache Memories.
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- Journal of Low Power Electronics & Applications, 2015, v. 5, n. 3, p. 165, doi. 10.3390/jlpea5030165
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A cache coherence protocol for distributed memory platforms.
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- Computer Systems Science & Engineering, 2010, v. 25, n. 5, p. 343
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ASYNCHRONOUS INSTRUCTION CACHE MEMORY FOR AVERAGE-CASE PERFORMANCE.
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- Journal of Circuits, Systems & Computers, 2014, v. 23, n. 5, p. -1, doi. 10.1142/S0218126614500637
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Hardware-Based Implementation of Algorithms for Data Replacement in Cache Memory of Processor Cores.
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- Computers (2073-431X), 2024, v. 13, n. 7, p. 166, doi. 10.3390/computers13070166
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DEPENDABILITY ASPECTS REGARDING THE DESIGN OF A CACHE MEMORY.
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- Annals of DAAAM & Proceedings, 2010, p. 645
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Quantum cache memory: a framework for enhancing DNA analysis through quantum computing.
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- Quantum Information Processing, 2024, v. 23, n. 12, p. 1, doi. 10.1007/s11128-024-04595-4
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- Article
Optimization of ETL Process in Data Warehouse Through a Combination of Parallelization and Shared Cache Memory.
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- Engineering, Technology & Applied Science Research, 2016, v. 6, n. 6, p. 1241, doi. 10.48084/etasr.849
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VMBKS: a shared memory cache system based on booting kernel in cloud.
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- Journal of Supercomputing, 2019, v. 75, n. 1, p. 4, doi. 10.1007/s11227-015-1554-1
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- Article
Compact and High-Speed Hsiao-Based SEC-DED Codec for Cache Memory.
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- Journal of Circuits, Systems & Computers, 2022, v. 31, n. 1, p. 1, doi. 10.1142/S0218126622500049
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Code integrity verification using cache memory monitoring.
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- Information Security Journal: A Global Perspective, 2022, v. 31, n. 2, p. 226, doi. 10.1080/19393555.2021.1902592
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AN INTEGRATED SIMULATION INFRASTRUCTURE FOR THE ENTIRE MEMORY HIERARCHY: CACHE , DRAM, NONVOLATI LE MEMORY, AND DISK.
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- Intel Technology Journal, 2013, v. 17, n. 1, p. 184
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Dynamic Partitioning of Shared Cache Memory.
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- Journal of Supercomputing, 2004, v. 28, n. 1, p. 7, doi. 10.1023/B:SUPE.0000014800.27383.8f
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Cache-Sensitive Memory Layout for Dynamic Binary Trees.
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- Computer Journal, 2016, v. 59, n. 5, p. 630, doi. 10.1093/comjnl/bxv090
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Cost aware cache replacement policy in shared last-level cache for hybrid memory based fog computing.
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- Enterprise Information Systems, 2018, v. 12, n. 4, p. 435, doi. 10.1080/17517575.2017.1295321
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ENHANCED PERFORMANCE OF CACHE MEMORY.
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- International Journal of Advanced Research in Computer Science, 2018, v. 9, n. 3, p. 34, doi. 10.26483/ijarcs.v9i3.5952
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Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers.
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- Computers, Materials & Continua, 2022, v. 73, n. 2, p. 2313, doi. 10.32604/cmc.2022.029019
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Dual-Port Content Addressable Memory for Cache Memory Applications.
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- Computers, Materials & Continua, 2022, v. 70, n. 3, p. 4583, doi. 10.32604/cmc.2022.020529
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Multiple cache recovery task cannot determine memory mechanisms.
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- Learning & Behavior, 2024, v. 52, n. 4, p. 291, doi. 10.3758/s13420-023-00616-x
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An efficient racetrack memory for L2 cache in GPGPUs.
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- Computer Systems Science & Engineering, 2017, v. 32, n. 6, p. 461
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Fast In-Memory Key–Value Cache System with RDMA.
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- Journal of Circuits, Systems & Computers, 2019, v. 28, n. 5, p. N.PAG, doi. 10.1142/S0218126619500749
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An Enhancement of Futures Runtime in Presence of Cache Memory Hierarchy.
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- Journal of Computing & Information Technology, 2008, v. 16, n. 4, p. 339, doi. 10.2498/cit.1001403
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Snooping protocol proposal to Improve Cache Performance via Reducing Memory Access Time.
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- Diyala Journal for Pure Science, 2019, v. 15, n. 3, p. 1, doi. 10.24237/djps.15.03.379C
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Proposed Design of 1 KB Memory Array Structure for Cache Memories.
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- Wireless Personal Communications, 2019, v. 109, n. 2, p. 823, doi. 10.1007/s11277-019-06593-7
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Word Sense Disambiguation Model with a Cache-Like Memory Module.
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- Journal of Donghua University (English Edition), 2021, v. 38, n. 4, p. 333, doi. 10.19884/j.1672-5220.202012114
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Reliability Increasing Method Using a SEC-DED Hsiao Code to Cache Memories, Implemented with FPGA Circuits.
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- Journal of Computer Science & Control Systems, 2011, v. 4, n. 2, p. 59
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Analytical Model For a Multiprocessor With Private Caches And Shared Memory.
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- International Journal of Computers, Communications & Control, 2008, v. 3, n. 2, p. 172, doi. 10.15837/ijccc.2008.2.2385
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Memory Map: A Multiprocessor Cache Simulator.
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- Journal of Electrical & Computer Engineering, 2012, p. 1, doi. 10.1155/2012/365091
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The memory behavior of cache oblivious stencil computations.
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- Journal of Supercomputing, 2007, v. 39, n. 2, p. 93, doi. 10.1007/s11227-007-0111-y
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Dynamic Partitioned Cache Memory for Real-Time MPSoCs with Mixed Criticality.
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- Journal of Circuits, Systems & Computers, 2016, v. 25, n. 6, p. -1, doi. 10.1142/S0218126616500626
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Asynchronous Adaptive Delay Tolerant Index Cache Using In-memory Delta Cell.
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- Informatica (03505596), 2015, v. 39, n. 4, p. 443
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A Quantitative Study of Locality in GPU Caches for Memory-Divergent Workloads.
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- International Journal of Parallel Programming, 2022, v. 50, n. 2, p. 189, doi. 10.1007/s10766-022-00729-2
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Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory.
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- International Journal of Parallel Programming, 2007, v. 35, n. 2, p. 157, doi. 10.1007/s10766-006-0030-1
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Hierarchical Binary Set Partitioning in Cache Memories.
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- Journal of Supercomputing, 2005, v. 31, n. 2, p. 185, doi. 10.1007/s11227-005-0106-5
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- Article
An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms.
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- International Journal of Reconfigurable Computing, 2011, p. 1, doi. 10.1155/2011/219497
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- Article
Carbon Nanotube Based Variation Tolerant Low Power Cache Memory for 5G Networks.
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- Iranian Journal of Electrical & Electronic Engineering, 2024, v. 20, n. 2, p. 1
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RELIABILITTY ASPECTS REGARDING THE CACHE LEVEL OF A MEMORY HIERARCHY.
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- Annals of DAAAM & Proceedings, 2009, p. 1137
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Studies on the energy and deep memory behaviour of a cache-oblivious, task-based hyperbolic PDE solver.
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- International Journal of High Performance Computing Applications, 2019, v. 33, n. 5, p. 973, doi. 10.1177/1094342019842645
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LDF (less dirty first): dirtiness-aware cache replacement policy for PCM main memory.
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- Electronics Letters (Wiley-Blackwell), 2013, v. 49, n. 25, p. 1607, doi. 10.1049/el.2013.1418
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What is the nature of cache memory in Parids? A comment on Chettih et al. 2024.
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- Animal Cognition, 2025, v. 28, n. 1, p. 1, doi. 10.1007/s10071-025-01932-7
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An Improved Memory Cache Management Study Based on Spark.
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- Computers, Materials & Continua, 2018, v. 56, n. 3, p. 415, doi. 10.3970/cmc.2018.03716
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A page replacement algorithm based on a fuzzy approach to improve cache memory performance.
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- Soft Computing - A Fusion of Foundations, Methodologies & Applications, 2020, v. 24, n. 2, p. 955, doi. 10.1007/s00500-019-04624-w
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UHNVM: A Universal Heterogeneous Cache Design with Non-Volatile Memory.
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- Electronics (2079-9292), 2021, v. 10, n. 15, p. 1760, doi. 10.3390/electronics10151760
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Comparative Analysis of Spintronic Memories for Low Power on-chip Caches.
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- SPIN (2010-3247), 2020, v. 10, n. 4, p. N.PAG, doi. 10.1142/S2010324720500277
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