Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW).

Lau, J. H.; Zhan, C.-J.; Tzeng, P.-J.; Lee, C.-K.; Dai, M.-J.; Chien, H.-C.; Chao, Y.-L.; Li, W.; Wu, S.-T.; Hung, J.-F.; Tain, R.-M.; Lin, C.-H.; Hsin, Y.-C.; Chen, C.-C.; Chen, S.-C.; Wu, C.-Y.; Chen, J.-C.; Chien, C.-H.; Chiang, C.-W.; Chang, H.-H.

The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with an RDL (redistribution layer) on both sides, IPD (integrated passive devices), and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and is then overmolded on its top side for pick and place purposes. The interposer's bottom side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly, and reliability are highlighted.

THERMAL management (Electronic packaging); ELECTRONIC packaging; FEASIBILITY studies; EXCHANGE reactions; PASSIVE components

Journal of Microelectronic & Electronic Packaging, 2011, Vol 8, Issue 4, p171

1551-4897

Academic Journal

10.4071/imaps.306