Works matching DE "ADDERS (Digital electronics)"

Results: 81

Design And Analysis Of 1-Bit Full Adder Using Cntfets.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2020, v. 2, n. 1, p. 14, doi. 10.31838/jvcs/02.01.04

By:

J., MURALIDHARAN

Publication type:

Article

Energy Efficient and Low Power Rca Based Full Adder.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2020, v. 2, n. 1, p. 6, doi. 10.31838/jvcs/02.01.02

By:

WATRIANTHOS, RONAL

Publication type:

Article

An Architecture of 2-Dimensional 4-Dot 2-Electron QCA Full Adder and Subtractor with Energy Dissipation Study.

Published in:

Active & Passive Electronic Components, 2018, p. 1, doi. 10.1155/2018/5062960

By:

Abdullah-Al-Shafi, Md.;
Bahar, Ali Newaz

Publication type:

Article

Principle and design of ternary optical accumulator implementing M-k-B addition.

Published in:

Optical Engineering, 2014, v. 53, n. 9, p. 1, doi. 10.1117/1.OE.53.9.095108

By:

Yunfu Shen;
Benpeng Jiang;
Yi Jin;
Ouyang Shan;
Junjie Peng

Publication type:

Article

Two Novel Quantum-Dot Cellular Automata Full Adders.

Published in:

Journal of Engineering (2314-4912), 2013, p. 1, doi. 10.1155/2013/561651

By:

Qanbari, Mahdie;
Sabbaghi-Nadooshan, Reza

Publication type:

Article

Design of novel efficient adder and subtractor for quantum-dot cellular automata.

Published in:

International Journal of Circuit Theory & Applications, 2015, v. 43, n. 10, p. 1446, doi. 10.1002/cta.2019

By:

Hayati, Mohsen;
Rezaei, Abbas

Publication type:

Article

A framework for high-speed parallel-prefix adder performance evaluation and comparison.

Published in:

International Journal of Circuit Theory & Applications, 2015, v. 43, n. 10, p. 1474, doi. 10.1002/cta.2020

By:

Hobson, Richard F.

Publication type:

Article

Simplified carry save adder-based array multiplier scheme and circuits design.

Published in:

International Journal of Circuit Theory & Applications, 2015, v. 43, n. 9, p. 1226, doi. 10.1002/cta.1998

By:

Jia, Song;
Lyu, Shigong;
Li, Xiayu;
Liu, Li;
He, Yandong

Publication type:

Article

Design of high-speed low-power parallel-prefix adder trees in nanometer technologies.

Published in:

International Journal of Circuit Theory & Applications, 2014, v. 42, n. 7, p. 731, doi. 10.1002/cta.1886

By:

Perri, Stefania;
Lanuzza, Marco;
Corsonello, Pasquale

Publication type:

Article

Alternative Approach of Developing Optical Binary Adder Using Reversible Peres Gates.

Published in:

International Journal of Optics, 2018, p. 1, doi. 10.1155/2018/8541371

By:

Mandal, Dhoumendra;
Mandal, Sumana;
Mandal, Mrinal Kanti;
Garai, Sisir Kumar

Publication type:

Article

A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology.

Published in:

Circuits, Systems & Signal Processing, 2015, v. 34, n. 3, p. 739, doi. 10.1007/s00034-014-9887-1

By:

Safaei Mehrabani, Yavar;
Eshghi, Mohammad

Publication type:

Article

Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology.

Published in:

2015

By:

Safaei Mehrabani, Yavar;
Eshghi, Mohammad

Publication type:

Erratum

A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures.

Published in:

Circuits, Systems & Signal Processing, 2014, v. 33, n. 6, p. 1689, doi. 10.1007/s00034-013-9727-8

By:

Aksoy, Levent;
Flores, Paulo;
Monteiro, José

Publication type:

Article

Designing Dynamic Carry Skip Adders: Analysis and Comparison.

Published in:

Circuits, Systems & Signal Processing, 2014, v. 33, n. 4, p. 1019, doi. 10.1007/s00034-013-9688-y

By:

Rose, Raffaele;
Lanuzza, Marco;
Frustaci, Fabio;
Purohit, Sohan

Publication type:

Article

A Novel CNTFET-based Ternary Full Adder.

Published in:

Circuits, Systems & Signal Processing, 2014, v. 33, n. 3, p. 665, doi. 10.1007/s00034-013-9672-6

By:

Keshavarzian, Peiman;
Sarikhani, Rahil

Publication type:

Article

DLPA: Discrepant Low PDP 8-Bit Adder.

Published in:

Circuits, Systems & Signal Processing, 2013, v. 32, n. 1, p. 1, doi. 10.1007/s00034-012-9438-6

By:

Ghadiry, Mahdiar;
Nadi, Mahdieh;
A'Ain, Abu

Publication type:

Article

Comparative Analysis of 8-Bit Adder Cells Using CLRCL Full Adder Logic.

Published in:

GSTF Journal on Computing, 2014, v. 3, n. 4, p. 104, doi. 10.7603/s40601-013-0046-5

By:

Kumar, Keshav;
Grover, Amit;
Grover, Neeti

Publication type:

Article

Formal Analysis of Hybrid Prefix/Carry-Select Arithmetic Systems.

Published in:

Computer Journal, 2011, v. 54, n. 6, p. 894, doi. 10.1093/comjnl/bxq048

By:

Liu, Feng;
Song, Xiaoyu;
Tan, Qingping;
Chen, Gang

Publication type:

Article

High Performance CNFET-based Ternary Full Adders.

Published in:

IETE Journal of Research, 2018, v. 64, n. 1, p. 108, doi. 10.1080/03772063.2017.1338973

By:

Sharifi, Fazel;
Panahi, Atiyeh;
Moaiyeri, Mohammad Hossein;
Sharifi, Hojjat;
Navi, Keivan

Publication type:

Article

A Physics-Based Model of Double-Gate Tunnel FET for Circuit Simulation.

Published in:

IETE Journal of Research, 2016, v. 62, n. 3, p. 387, doi. 10.1080/03772063.2015.1082443

By:

Narendiran, A.;
Akhila, K.;
Bindu, B.

Publication type:

Article

Implementing a one-bit reversible full adder using quantum-dot cellular automata.

Published in:

Quantum Information Processing, 2014, v. 13, n. 9, p. 2127, doi. 10.1007/s11128-014-0782-2

By:

Mohammadi, Zahra;
Mohammadi, Majid

Publication type:

Article

Fast arithmetic in algorithmic self-assembly.

Published in:

Natural Computing, 2016, v. 15, n. 1, p. 115, doi. 10.1007/s11047-015-9512-7

By:

Keenan, Alexandra;
Schweller, Robert;
Sherman, Michael;
Zhong, Xingsi

Publication type:

Article

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures.

Published in:

VLSI Design, 2013, p. 1, doi. 10.1155/2013/785281

By:

Olivieri, Mauro;
Mastrandrea, Antonio

Publication type:

Article

Faster and Energy-Efficient Signed Multipliers.

Published in:

VLSI Design, 2013, p. 1, doi. 10.1155/2013/495354

By:

Ramkumar, B.;
Kittur, Harish M.

Publication type:

Article

FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders.

Published in:

VLSI Design, 2013, p. 1, doi. 10.1155/2013/382682

By:

Hoe, David H. K.;
Bollepalli, L. P. Deepthi;
Martinez, Chris D.

Publication type:

Article

Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL.

Published in:

VLSI Design, 2013, p. 1, doi. 10.1155/2013/157872

By:

Kumar, A. Kishore;
Somasundareswari, D.;
Duraisamy, V.;
Pradeepa, T. Shunbaga

Publication type:

Article

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders.

Published in:

VLSI Design, 2012, p. 1, doi. 10.1155/2012/575389

By:

Balasubramanian, P.;
Edwards, D. A.;
Toms, W. B.

Publication type:

Article

Efficient Fused MAC Unit Using Multi-Operand Parallel Prefix Adder.

Published in:

Radioelectronics & Communications Systems, 2022, v. 65, n. 4, p. 213, doi. 10.3103/S0735272722040057

By:

Abinaya, A.;
Maheswari, M.

Publication type:

Article

Low-Power Modified Shift-Add Multiplier Design Using Parallel Prefix Adder.

Published in:

Journal of Circuits, Systems & Computers, 2019, v. 28, n. 2, p. N.PAG, doi. 10.1142/S0218126619500191

By:

Pinto, Rohan;
Shama, Kumara

Publication type:

Article

A 0.6V 19.5W 80dB DR Modulator with SA-Quantizers and Digital Feedforward Path.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 7, p. -1, doi. 10.1142/S0218126617501171

By:

Chen, Hongmei;
Wang, Li;
Li, Ting;
He, Lin;
Lin, Fujiang

Publication type:

Article

Design and Implementation of 32-Bit High Valency Jackson Adders.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 7, p. -1, doi. 10.1142/S0218126617501237

By:

Poornima, N.;
Bhaaskaran, V. S. Kanchana

Publication type:

Article

A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500827

By:

Mehrabani, Yavar Safaei;
Mirzaee, Reza Faghih;
Zareei, Zahra;
Daryabari, Seyedeh Mohtaram

Publication type:

Article

An Energy Efficient Logic Approach to Implement CMOS Full Adder.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500840

By:

Kumar, Pankaj;
Sharma, Rajender Kumar

Publication type:

Article

Efficient Realization of Fixed-Point Binary and Ternary Adders on FPGAs.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 4, p. -1, doi. 10.1142/S0218126617500530

By:

Khurshid, Burhan;
Naaz, Roohie

Publication type:

Article

Multistage Latency Adders Architecture Employing Approximate Computing.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 3, p. -1, doi. 10.1142/S0218126617500396

By:

Yang, Xinghua;
Xing, Yue;
Qiao, Fei;
Yang, Huazhong

Publication type:

Article

Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 1, p. 1, doi. 10.1142/S0218126617500141

By:

Parameshwara, M. C.;
Srinivasaiah, H. C.

Publication type:

Article

Modified Operand Decomposition Multiplication for High Performance Parallel Multipliers.

Published in:

Journal of Circuits, Systems & Computers, 2016, v. 25, n. 12, p. -1, doi. 10.1142/S0218126616501498

By:

Abid, Z.;
El-Dib, Dalia A.;
Mudassir, Rizwan

Publication type:

Article

A Low-Power and Area-Efficient 64-Bit Digital Comparator.

Published in:

Journal of Circuits, Systems & Computers, 2016, v. 25, n. 12, p. -1, doi. 10.1142/S0218126616501486

By:

Vijaya Krishna Boppana, N. V.;
Ren, Saiyu

Publication type:

Article

Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic.

Published in:

Journal of Circuits, Systems & Computers, 2016, v. 25, n. 7, p. -1, doi. 10.1142/S0218126616500730

By:

Singhal, Subodh Kumar;
Mohanty, Basant Kumar

Publication type:

Article

Efficient Audio Filter Using Folded Pipelining Architecture Based on Retiming Using Evolutionary Computation.

Published in:

Journal of Circuits, Systems & Computers, 2015, v. 24, n. 5, p. -1, doi. 10.1142/S0218126615500681

By:

Yagain, Deepa;
Balla, Sivanag;
Krishna, Vijaya

Publication type:

Article

SELF-TIMED SECTION-CARRY BASED CARRY LOOKAHEAD ADDERS AND THE CONCEPT OF ALIAS LOGIC.

Published in:

Journal of Circuits, Systems & Computers, 2013, v. 22, n. 4, p. 1, doi. 10.1142/S021812661350028X

By:

BALASUBRAMANIAN, P.;
EDWARDS, D. A.;
TOMS1, W. B.

Publication type:

Article

MULTIFUNCTION RNS MODULO 2<sup>n</sup> ± 1 MULTIPLIERS.

Published in:

Journal of Circuits, Systems & Computers, 2012, v. 21, n. 4, p. -1, doi. 10.1142/S0218126612500272

By:

JUANG, TSO-BING;
KUO, CHAO-TSUNG;
WU, GO-LONG;
HUANG, JIAN-HAO

Publication type:

Article

Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints.

Published in:

Journal of Electronic Testing, 2018, v. 34, n. 1, p. 7, doi. 10.1007/s10836-017-5701-x

By:

Salehi, Mostafa;
Azarpeyvand, Ali;
Aboutalebi, Armin Hajaboutalebi

Publication type:

Article

Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic.

Published in:

Electronics (2079-9292), 2018, v. 7, n. 10, p. 243, doi. 10.3390/electronics7100243

By:

Balasubramanian, Padmanabhan;
Maskell, Douglas;
Mastorakis, Nikos

Publication type:

Article

High Performance DIF-FFT Using Dissimilar Partitioned LUT Based Distributed Arithmetic.

Published in:

International Journal of Electronics & Telecommunications, 2021, v. 67, n. 4, p. 631, doi. 10.24425/ijet.2021.137856

By:

Cheepurupalli, Kusma Kumari;
Charan, Muntha;
Rao, Jammu Bhaskara;
Noor, Mahammad S.

Publication type:

Article

SPEED COMPARISON OF THE ADDERS IN FPGA.

Published in:

Science & Military Journal, 2013, v. 8, n. 1, p. 18

By:

TURČANÍK, Michal

Publication type:

Article

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing.

Published in:

International Journal of Theoretical Physics, 2018, v. 57, n. 5, p. 1356, doi. 10.1007/s10773-018-3664-z

By:

Bilal, Bisma;
Ahmed, Suhaib;
Kakkar, Vipan

Publication type:

Article

A Three-Layer Full Adder/Subtractor Structure in Quantum-Dot Cellular Automata.

Published in:

International Journal of Theoretical Physics, 2017, v. 56, n. 9, p. 2848, doi. 10.1007/s10773-017-3453-0

By:

Barughi, Yashar;
Heikalabad, Saeed

Publication type:

Article

On Design of Parity Preserving Reversible Adder Circuits.

Published in:

International Journal of Theoretical Physics, 2016, v. 55, n. 12, p. 5118, doi. 10.1007/s10773-016-3133-5

By:

Haghparast, Majid;
Bolhassani, Ali

Publication type:

Article

Optimally Factored IFIR Filters.

Published in:

Circuits, Systems & Signal Processing, 2019, v. 38, n. 1, p. 259, doi. 10.1007/s00034-018-0857-x

By:

Mehrnia, A.;
Willson, A. N.

Publication type:

Article