An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder.

Tran-Thi, Bich Ngoc; Nguyen-Ly, Thien Truong; Hoang, Trang

A hardware-efficient implementation of a Low-Density Parity-Check (LDPC) decoder is presented in this paper. The proposed decoder design is based on the Hybrid Offset Min-Sum (HOMS) algorithm. In the check node processing of this decoder, only the first minimum is computed instead of the first two minimum values among all the variable-to-check message inputs as in the conventional approach. Additionally, taking advantage of the unique structure of 5G LDPC codes, layered scheduling and partially parallel structures are employed to minimize hardware costs. Implementation results on the Xilinx Kintex UltraScale+ FPGA platform show that the proposed decoder can achieve a throughput of 2.82 Gbps for 10 decoding iterations with a 5G LDPC codelength of 8832 bits and a code rate of 1/2. Moreover, it yields a check node memory reduction of 10% with respect to the baseline and provides a hardware usage efficiency of 4.96 hardware resources/layer/Mbps, while providing a decoding performance of 0.15 dB better than some of the existing decoders.

5G networks; LOW density parity check codes; FIELD programmable gate arrays; BIT rate; BIT error rate

Electronics (2079-9292), 2023, Vol 12, Issue 17, p3667

2079-9292

Academic Journal

10.3390/electronics12173667