Works matching IS 25821458 AND DT 2024 AND VI 6 AND IP 1

Results: 9

Design and VLSI implementation of SAR Analog to Digital Converter Using Analog Mixed Signal.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 55, doi. 10.31838/jvcs/06.01.05

By:

N., Megha;
Shetty, Prajwal;
Kudtarkar, Rahul R.;
Naik, Siddesh U.;
Abhilash, A. L.

Publication type:

Article

A Low Power Adiabatic Approach for Scaled VLSI Circuits.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 1, doi. 10.31838/jvcs/06.01.01

By:

Bhowmik, Sabarni;
Majumder, Tanmoy;
Bhattacharjee, Abhishek

Publication type:

Article

51 Smart Ways to Catch the Abutment DRCs at IP Level.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 51, doi. 10.31838/jvcs/06.01.08

By:

Kulkarni, Swanand;
J. N., Ravi

Publication type:

Article

Low Power Embedded SoC Design.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 25, doi. 10.31838/jvcs/06.01.04

By:

Sasikala, G.;
Krishna, G. Satya

Publication type:

Article

1.8-V Low Power, High-Resolution, High-Speed Comparator With Low Offset Voltage Implemented in 45nm CMOS Technology.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 19, doi. 10.31838/jvcs/06.01.03

By:

Mukti, Ishrat Z.;
Khan, Ebadur R.;
Biswas, Koushik K.

Publication type:

Article

Detection of Soft Errors in Clock Synthesizers and Latency Reduction Throgh Voltage Scaling Mechanism.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 43, doi. 10.31838/jvcs/06.01.08

By:

Arshath, N. Mohamed

Publication type:

Article

A Hybrid Optical-Acoustic Modem Based on Mimo-Ofdm for Reliable Data Transmission in Green Underwater Wireless Communication.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 36, doi. 10.31838/jvcs/06.01.06

By:

Pallavi, CH.;
Sreenivasulu, G.

Publication type:

Article

Desing of VLSI Architecture for a flexible testbed of Artificial Neural Network for training and testing on FPGA.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 30, doi. 10.31838/jvcs/06.01.06

By:

Arora, Gurmeet Kaur

Publication type:

Article

Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 7, doi. 10.31838/jvcs/06.01.02

By:

Pakkiraiah, C.;
Satyanarayana, R. V. S.

Publication type:

Article