SPEED COMPARISON OF THE ADDERS IN FPGA.
- Published in:
- Science & Military Journal, 2013, v. 8, n. 1, p. 18
- By:
- Publication type:
- Article
Works matching DE "SUMMING circuits"
Results: 7
1
2
The application of improved signal summing method into the spacecraft force limited vibration test.
- Published in:
- Journal of Vibroengineering, 2017, v. 19, p. 23, doi. 10.21595/vp.2017.19163
- By:
- Publication type:
- Article
3
Efficient Fused MAC Unit Using Multi-Operand Parallel Prefix Adder.
- Published in:
- Radioelectronics & Communications Systems, 2022, v. 65, n. 4, p. 213, doi. 10.3103/S0735272722040057
- By:
- Publication type:
- Article
4
Designing Dynamic Carry Skip Adders: Analysis and Comparison.
- Published in:
- Circuits, Systems & Signal Processing, 2014, v. 33, n. 4, p. 1019, doi. 10.1007/s00034-013-9688-y
- By:
- Publication type:
- Article
5
Design And Analysis Of 1-Bit Full Adder Using Cntfets.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2020, v. 2, n. 1, p. 14, doi. 10.31838/jvcs/02.01.04
- By:
- Publication type:
- Article
6
Energy Efficient and Low Power Rca Based Full Adder.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2020, v. 2, n. 1, p. 6, doi. 10.31838/jvcs/02.01.02
- By:
- Publication type:
- Article
7
QPSK Modulator with Continuous Phase and Fast Response Based on Phase-Locked Loop.
- Published in:
- Radioengineering, 2017, v. 26, n. 2, p. 504, doi. 10.13164/re.2017.0504
- By:
- Publication type:
- Article