A GENTLE INTRODUCTION TO S-NET:: TYPED STREAM PROCESSING AND DECLARATIVE COORDINATION OF ASYNCHRONOUS COMPONENTS.
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- Parallel Processing Letters, 2008, v. 18, n. 2, p. 221, doi. 10.1142/S0129626408003351
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Works matching IS 01296264 AND DT 2008 AND VI 18 AND IP 2
Results: 9
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ON DESIGN AND APPLICATION MAPPING OF A NETWORK-ON-CHIP(NOC) ARCHITECTURE.
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- Parallel Processing Letters, 2008, v. 18, n. 2, p. 239, doi. 10.1142/S0129626408003363
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ADAPTIVE COMMUNICATION ARCHITECTURES FOR RUNTIME RECONFIGURABLE SYSTEM-ON-CHIPS.
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- Parallel Processing Letters, 2008, v. 18, n. 2, p. 275, doi. 10.1142/S0129626408003387
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- Article
4
EDITORIAL NOTE.
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- Parallel Processing Letters, 2008, v. 18, n. 2, p. 201, doi. 10.1142/S0129626408003326
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GUEST EDITOR'S INTRODUCTION.
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- Parallel Processing Letters, 2008, v. 18, n. 2, p. 203, doi. 10.1142/S0129626408003338
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- Article
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OPERATING SYSTEMS IN SILICON AND THE DYNAMIC MANAGEMENT OF RESOURCES IN MANY-CORE CHIPS.
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- Parallel Processing Letters, 2008, v. 18, n. 2, p. 257, doi. 10.1142/S0129626408003375
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7
Rapid Prototyping of the Data-Driven Chip-Multiprocessor (D<sup>2</sup>-CMP) using FPGAs.
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- Parallel Processing Letters, 2008, v. 18, n. 2, p. 291, doi. 10.1142/S0129626408003399
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8
MODELING THE PERFORMANCE OF COMMUNICATION SCHEMES ON NETWORK TOPOLOGIES.
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- Parallel Processing Letters, 2008, v. 18, n. 2, p. 205, doi. 10.1142/S012962640800334X
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9
AN ORDER DEGREE ALTERNATOR FOR ARBITRARY TOPOLOGIES.
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- Parallel Processing Letters, 2008, v. 18, n. 2, p. 307, doi. 10.1142/S0129626408003405
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- Article