Works matching DE "COMPUTER hardware description languages"
Results: 180
Decodificador Turbo MAP de varias iteraciones.
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- Ingeniería y Desarrollo, 2006, n. 20, p. 106
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Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA.
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- Wireless Personal Communications, 2014, v. 76, n. 3, p. 569, doi. 10.1007/s11277-014-1725-z
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Design a Vedic Multiplier using Xilinx Vivado.
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- Grenze International Journal of Engineering & Technology (GIJET), 2024, v. 10, n. 1, Part 3, p. 2218
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A Parallel Yet Pipelined Architecture for Efficient Implementation of the Advanced Encryption Standard Algorithm on Reconfigurable Hardware.
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- International Journal of Parallel Programming, 2016, v. 44, n. 6, p. 1102, doi. 10.1007/s10766-016-0408-7
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Power Efficiency for Hardware/Software Partitioning with Time and Area Constraints on MPSoC.
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- International Journal of Parallel Programming, 2015, v. 43, n. 3, p. 381, doi. 10.1007/s10766-013-0283-4
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LALP: A Language to Program Custom FPGA-Based Acceleration Engines.
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- International Journal of Parallel Programming, 2012, v. 40, n. 3, p. 262, doi. 10.1007/s10766-011-0187-0
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Supporting Microthread Scheduling and Synchronisation in CMPs.
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- International Journal of Parallel Programming, 2006, v. 34, n. 4, p. 343, doi. 10.1007/s10766-006-0017-y
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Language and Compiler Design for Streaming Applications.
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- International Journal of Parallel Programming, 2005, v. 33, n. 2/3, p. 261, doi. 10.1007/s10766-005-3590-6
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An Efficient QC-LDPC Decoder Architecture for 5G-NR Wireless Communication Standards Targeting FPGA.
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- Computers (2073-431X), 2024, v. 13, n. 8, p. 195, doi. 10.3390/computers13080195
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DESIGN MODELS OF BIT-STREAM ONLINE-COMPUTERS FOR SENSOR COMPONENTS.
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- Radio Electronics, Computer Science, Control, 2024, n. 1, p. 62, doi. 10.15588/1607-3274-2024-1-6
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TEMPORAL EVENTS PROCESSING MODELS IN FINITE STATE MACHINES.
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- Radio Electronics, Computer Science, Control, 2023, n. 4, p. 49, doi. 10.15588/1607-3274-2023-4-5
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Efficient Hardware Accelerator and Implementation of JPEG 2000 MQ Decoder Architecture.
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- Engineering, Technology & Applied Science Research, 2024, v. 14, n. 2, p. 13463, doi. 10.48084/etasr.7065
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Hardware efficient reconfigurable digital down converter for software radio receiver.
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- International Journal of Electronics Letters, 2024, v. 12, n. 2, p. 107, doi. 10.1080/21681724.2023.2192964
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Design and Implementation of a Real-Time Image Processing System Based on Sobel Edge Detection using Model-based Design Methods.
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- International Journal of Advanced Computer Science & Applications, 2024, v. 15, n. 3, p. 273, doi. 10.14569/ijacsa.2024.0150328
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FPGA-based Implementation of a Resource-Efficient UNET Model for Brain Tumour Segmentation.
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- International Journal of Advanced Computer Science & Applications, 2024, v. 15, n. 1, p. 622, doi. 10.14569/ijacsa.2024.0150161
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Signed real measure of regular languages for discrete-event automata.
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- International Journal of Control, 2003, v. 76, n. 18, p. 1800, doi. 10.1080/00207170310001635392
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Hardware Inexact Grammar Parser.
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- International Journal of Pattern Recognition & Artificial Intelligence, 2017, v. 31, n. 11, p. -1, doi. 10.1142/S021800141759025X
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Parallel Hardware Stochastic Context-Free Parsers.
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- International Journal of Pattern Recognition & Artificial Intelligence, 2016, v. 30, n. 4, p. -1, doi. 10.1142/S0218001416500087
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Formal semantics analysis for VHDL RTL synthesis.
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- Computer Systems Science & Engineering, 2003, v. 18, n. 6, p. 357
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Optimized pure hardware FPGA-based implementation of active disturbance rejection control.
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- Electrical Engineering, 2018, v. 100, n. 1, p. 111, doi. 10.1007/s00202-016-0495-x
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Mutation Testing for Effective Verification of Digital Components of Physical Systems.
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- Russian Physics Journal, 2015, v. 58, n. 8, p. 1128, doi. 10.1007/s11182-015-0622-6
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- Article
Computational Modeling of Cell Survival Using VHDL.
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- BVICAM's International Journal of Information Technology, 2010, v. 2, n. 1, p. 53
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LabVIEW FPGA Implementation Of a PID Controllerb For D.C. Motor Speed Control.
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- Iraqi Journal for Electrical & Electronic Engineering, 2010, v. 6, n. 1, p. 139, doi. 10.33762/eeej.2010.54884
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DESCRIPTIONAL COMPLEXITY OF SPLICING SYSTEMS.
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- International Journal of Foundations of Computer Science, 2008, v. 19, n. 4, p. 813, doi. 10.1142/S0129054108005978
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TESTING THE DESCRIPTIONAL POWER OF SMALL TURING MACHINES ON NONREGULAR LANGUAGE ACCEPTANCE.
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- International Journal of Foundations of Computer Science, 2008, v. 19, n. 4, p. 827, doi. 10.1142/S012905410800598X
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OPTIMAL RESULTS FOR THE COMPUTATIONAL COMPLETENESS OF GEMMATING (TISSUE) P SYSTEMS.
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- International Journal of Foundations of Computer Science, 2005, v. 16, n. 5, p. 929, doi. 10.1142/S0129054105003388
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RESTRICTED SETS OF TRAJECTORIES AND DECIDABILITY OF SHUFFLE DECOMPOSITIONS.
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- International Journal of Foundations of Computer Science, 2005, v. 16, n. 5, p. 897, doi. 10.1142/S0129054105003364
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THE PHENOMENON OF NON-RECURSIVE TRADE-OFFS.
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- International Journal of Foundations of Computer Science, 2005, v. 16, n. 5, p. 957, doi. 10.1142/S0129054105003406
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Improving dependability with low power fault detection model for skinny-hash.
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- PLoS ONE, 2024, v. 19, n. 12, p. 1, doi. 10.1371/journal.pone.0316012
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A calculus for hardware description.
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- Journal of Functional Programming, 2011, v. 21, n. 1, p. 21, doi. 10.1017/S0956796810000249
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Translation of tree-processing programs into stream-processing programs based on ordered linear type1.
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- Journal of Functional Programming, 2008, v. 18, n. 3, p. 333, doi. 10.1017/S0956796807006570
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- Article
A Real-Time Implementation Of An Autonomous Uav Controller Using Fpga: Based On Fuzzy Logic Approach.
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- International Journal of Simulation: Systems, Science & Technology, 2014, v. 15, n. 1, p. 37
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Manta: rapid detection of structural variants and indels for germline and cancer sequencing applications.
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- Bioinformatics, 2016, v. 32, n. 8, p. 1220, doi. 10.1093/bioinformatics/btv710
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LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure.
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- IPSJ Transactions on System LSI Design Methodology, 2023, v. 16, n. 1, p. 12, doi. 10.2197/ipsjtsldm.16.12
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Scalable Hardware Architecture for fast Gradient Boosted Tree Training.
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- IPSJ Transactions on System LSI Design Methodology, 2021, v. 14, n. 1, p. 11, doi. 10.2197/ipsjtsldm.14.11
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Low-cost embedded intelligent system design for smart mobile robot controller.
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- Przegląd Elektrotechniczny, 2023, v. 99, n. 3, p. 236, doi. 10.15199/48.2023.03.42
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- Article
Design and Optimization of a Petri Net-Based Concurrent Control System toward a Reduction in the Resources in a Field-Programmable Gate Array.
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- Applied Sciences (2076-3417), 2024, v. 14, n. 12, p. 5212, doi. 10.3390/app14125212
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Hardware Embedded Fiber Sensor Interrogation System using Intensive Digital Signal Processing.
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- Journal of Microwaves, Optoelectronics & Electromagnetic Applications, 2014, v. 13, n. 2, p. AoP29, doi. 10.1590/s2179-10742014000200003
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Modern analog and digital communication systems development using GNU Radio with USRP.
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- Telecommunication Systems, 2014, v. 56, n. 3, p. 367, doi. 10.1007/s11235-013-9850-7
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- Article
Radar-Jamming Decision-Making Based on Improved Q-Learning and FPGA Hardware Implementation.
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- Remote Sensing, 2024, v. 16, n. 7, p. 1190, doi. 10.3390/rs16071190
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- Article
AUTOMATED DEBUGGING OF VERILOG DESIGNS.
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- International Journal of Software Engineering & Knowledge Engineering, 2012, v. 22, n. 5, p. 695, doi. 10.1142/S0218194012500209
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- Article
Algorithm & Design of an Efficient Floating Point ADD/SUB Unit for an Experimental CPU.
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- International Journal of Intelligent Information Technology Application, 2009, v. 2, n. 6, p. 273
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- Article
OPEN SOURCE SEMICONDUCTOR CORE LICENSING.
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- Harvard Journal of Law & Technology, 2011, v. 25, n. 1, p. 131
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- Article
Machine Learning for Hardware Security: Opportunities and Risks.
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- Journal of Electronic Testing, 2018, v. 34, n. 2, p. 183, doi. 10.1007/s10836-018-5726-9
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- Article
Simulation-based Fault Injection with QEMU for Speeding-up Dependability Analysis of Embedded Software.
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- Journal of Electronic Testing, 2016, v. 32, n. 1, p. 43, doi. 10.1007/s10836-015-5555-z
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- Article
Verilog HDL Simulator Technology: A Survey.
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- Journal of Electronic Testing, 2014, v. 30, n. 3, p. 255, doi. 10.1007/s10836-014-5449-5
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Coverage metrics for formal verification.
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- International Journal on Software Tools for Technology Transfer, 2006, v. 8, n. 4/5, p. 373, doi. 10.1007/s10009-004-0175-4
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- Article
prialt in Handel-C: an operational semantics.
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- International Journal on Software Tools for Technology Transfer, 2005, v. 7, n. 3, p. 248, doi. 10.1007/s10009-004-0181-6
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- Article
Register Transfer Level Disparity generator with Stereo Vision.
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- Journal of Open Research Software, 2021, v. 9, n. 1, p. 1, doi. 10.5334/jors.339
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- Article
A Field-Programmable Gate Array-Based Quasi-Cyclic Low-Density Parity-Check Decoder with High Throughput and Excellent Decoding Performance for 5G New-Radio Standards.
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- Technologies (2227-7080), 2024, v. 12, n. 11, p. 215, doi. 10.3390/technologies12110215
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- Article